Abstract: A programmable logic device includes a non-volatile permission memory block to enable a customer to utilize a proprietary core. In one embodiment, the core supplier designs its core to check for a specified permission bit or bit pattern in the permission memory block before the core will operate. If the permission bit or bit pattern is set properly, the core functions correctly when implemented in the PLD. If not, the core will not function. To prevent the customer from modifying the core such that it no longer depends upon the permission bits to function, the configuration bitstream used to program the PLD can be encrypted before and during transmission to the PLD. This encryption ensures security of the customer's logic design as well as the supplier's core design. In this manner, the customer remains dependent upon properly set permission memory bits, i.e. proper authorization, to obtain core functionality.

Abstract: A novel method and corresponding system are provided for safely reconfiguring a portion of a reprogrammable logic device. The method includes the steps of identifying the nets to be reprogrammed, identifying the device drivers that may induce signal contention during or after a new configuration on the identified nets, electrically isolating the identified drivers, and implementing the new configuration.

Abstract: A method and apparatus are disclosed for reducing the likelihood of unintentionally or irreversibly activating one or more of a programmable logic device's output elements after a programming interruption. Output disable and enable bits are moved to near the beginning and end, respectively, of a programming bitstream, thereby maximizing the amount of time the device outputs are in high impedance mode during programming, and minimizing the risk of unintentionally driving the device outputs.

Abstract: A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

Abstract: A system and method are disclosed for providing highly parallel, FFT calculations in a circuit including a plurality of RADIX-2 elements. Partitioned RAM resources allow RADIXes at all stages to have optimal bandwidth memory access. Preferably more memory is made available for early RADIX stages and a “critical” stage. RADIXes within stages beyond the critical stage preferably each need only a single RAM partition, and can therefore simultaneously operate without fighting for memory resources. In a preferred configuration having P RAM partitions and P RADIX stages, the critical stage is stage number log2P, and until the critical stage, only P/2 RADIX elements can simultaneously operate within each stage. After the critical stage, all RADIXes within each stage can simultaneously operate.

Abstract: An input signal latching circuit for suppressing the effect of any ringing or other irregularities that occur within a specified time period after a transitional voltage level is reached, without significantly delaying the propagation of the input signal.

Abstract: A method and system for translating abstract structural or behavioral circuit descriptions to physically implementable files, preferably suitable for use in a Field Programmable Gate Array (FPGA) or other programmable device. A selection of layouts are generated for a cell definition (a function), allowing optimization and acceleration of circuit placement and routing without compromising design hierarchy or altering design function. Layout transformation functions may be manually initiated or automtically selected and applied during implementation of a placement algorithm.

Abstract: A method and software apparatus for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. A modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results.

Abstract: A novel system and method are provided for storing a configuration data file for a programmable logic device such as an FPGA and for loading such a file into the device. The system and method of the present invention improves the performance of a bitstream storage apparatus by compressing the bitstream by a factor of about 5:1 to 10:1 before loading the bitstream into a storage unit, and then decompressing the bitstream, preferably within the storage unit, before forwarding the bitstream to the programmable device. In one embodiment, the decompression circuit is programmable, being able to utilize any of two or more different algorithms. In this embodiment, several different compression algorithms are evaluated, and the most efficient algorithm for that particular bitstream is utilized.

Abstract: The invention provides a Field Programmable Gate Array (FPGA) that initiates its own reconfiguration by driving its own output terminal and its own connected PROGRAM input terminal, permitting reliable self-reconfiguration of the FPGA. The signal forwarded to the PROGRAM input terminal triggers a reconfiguration sequence that, in turn, causes the signal received from the output terminal to be ignored. Therefore, the method of the invention is reliably stable and does not undesirably repeat, oscillate, or fail. The FPGA may initiate its own reconfiguration upon detecting that a new configuration bitstream has been selected for downloading from an external device such as a PROM. The FPGA may detect the actuation of a binary or rotary switch. Alternatively, the FPGA may detect when a CMOS latch or register points to a new configuration address in the PROM. In one embodiment, an external memory device stores FPGA state information from one reconfiguration cycle to the next.

Abstract: A system and method for conducting a multi-person, interactive auction, in a variety of formats, without using a human auctioneer to conduct the auction. The system is preferably implemented in software. The system allows a group of bidders to interactively place bids over a computer or communications network. Those bids are recorded by the system and the bidders are updated with the current auction status information. When appropriate, the system closes the auction from further bidding and notifies the winning bidders and losers as to the auction outcome.

Abstract: A typical conventional Graphical User Interface (GUI) displays multiple menu items, together with their respective icons (or symbols), on a display region. However, when a display region has a relatively small area, displaying icons (or symbols) together with their respective menu items makes the display region clustered, thus increasing the difficulty for a user to locate and select a desired menu item. To overcome this shortcoming, an improved GUI displays multiple menu items of a menu on a display region that contains a column window and row window. Each of the menu items contains a content field and a symbol field. The GUI only displays the symbol fields of the menu items that are scrolled into the column window and the content field of a menu item that is scrolled into the row window. In doing so, the improved GUI facilitates a user to select a desired menu item from the menu.

Abstract: A modification to the available simulated annealing algorithm is provided to better utilize direct connects and other architecture-specific features of a Field Programmable Gate Array. A preferred embodiment comprises adding a template-based move to the SA move-set that recognizes a specific pattern or template in the user's design after mapping, and arranges the components into the optimal configuration for the specific template discovered. The present invention increases the intelligence of the SA move-set by selectively supplementing the random moves in the move-set with moves that produce locally good solutions.

Abstract: A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

Abstract: A system and method are disclosed for providing highly parallel, FFT calculations in a circuit including a plurality of RADIX-2 elements. Partitioned RAM resources allow RADIXes at all stages to have optimal bandwidth memory access. Preferably more memory is made available for early RADIX stages and a "critical" stage. RADIXes within stages beyond the critical stage preferably each need only a single RAM partition, and can therefore simultaneously operate without fighting for memory resources. In a preferred configuration having P RAM partitions and P RADIX stages, the critical stage is stage number log.sub.2 P, and until the critical stage, only P/2 RADIX elements can simultaneously operate within each stage. After the critical stage, all RADIXes within each stage can simultaneously operate.

Abstract: A method for designing an integrated circuit comprises the step of selecting a system-level parameterized module that performs a specified type of function. The method also includes the steps of specifying values for parameters of the selected system-level module and generating a netlist file from the selected system-level module. In one embodiment, the system-level parameterized module is selected from a family of system-level parameterized modules that each perform a particular function within different parameter ranges.

Abstract: A decryption scheme is provided for encrypted configuration bitstreams in a programmable logic device. One embodiment includes circuitry for altering a decryption key for a plurality of encrypted bitstream portions, thereby providing a high level of security of the circuit layout embodied in the bitstream.

Abstract: A method of computer aided design of coarse grain FPGA's by employing a library of selected primitive cells, defining the connection classes useful in the FPGA design, and assigning appropriate connection classes to the inputs and outputs of the respective primitive cells. The primitive cells and defined interconnections used therein have accurately established timing and power parameters thereby enabling more accurate assessments of static timing and power consumption for the entire FPGA design. Moreover, the method of the present invention results in placement directives which then serve as connection criteria in carrying out subsequent place and route algorithms. One such placement directive is implemented as a "local output" (LO) of some of the primitive cells which implies that that particular output must be connected to another primitive cell input within the local configurable logic block (CLB). Another such placement directive is obtained by using a plurality of virtual buffers.

Abstract: A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks, interconnect, and routing wires may be accomplished with switch matrices and programmable interconnect points.

Abstract: A dynamically reconfigurable FPGA includes an array of tiles on a logic plane and a plurality of memory planes. Each tile has associated storage elements on each memory plane, called local memory. This local memory allows large amounts of data to pass from one FPGA configuration (memory plane) to another with no external memory access, thereby transferring data to/from the storage elements in the logic plane at very high speed. Typically, all the local memory can be simultaneously transferred to/from other memory planes in one cycle. Each FPGA configuration provides a virtual instruction. The present invention uses two different types of virtual instructions: computational and pattern manipulation instructions. Computational instructions perform some computation with data stored in some pre-defined local memory pattern. Pattern manipulation instructions move the local data into different memory locations to create the pattern required by the next instruction.