Abstract: A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary field programmable gate array chip without required off-chip memory for storing constants.

Abstract: A method and system for translating abstract structural or behavioral circuit descriptions to physically implementable files, preferably suitable for use in a Field Programmable Gate Array (FPGA) or other programmable device. A selection of layouts are generated for a cell definition (a function), allowing optimization and acceleration of circuit placement and routing without compromising design hierarchy or altering design function. Layout transformation functions may be manually initiated or automatically selected and applied during implementation of a placement algorithm.

Abstract: A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables permits the computation of vector rotation and large FFTs in an efficient-parallel fashion within a unitary field programmable gate array chip, without off-chip memory for storing constants.

Abstract: The notion of global signals (e.g., global set/reset and global tristate) is of significance to programmable logic user throughout the design process. Regardless of whether the HDL designer explicitly describes the use of a global signal, they are present in the implemented device since they are an integral part of the initialization and start-up process. This may lead to mismatches between the Register Transfer Level (RTL) simulation and the timing simulation. While a methodology for verifying the functionality of global signals is available for schematic design entry, none exists for HDL design tools. A verification method for HDL designers is disclosed providing access to all the functionality relating to global networks currently available to the schematic designers and allowing reuse of the testbench without losing HDL code portability.

Abstract: A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.

Abstract: A semiconductor testing system that performs real-time adjustment of programmed values for test signals using an interface between a system controller and the pin resources. The interface includes a calibration memory that contains timing offset values and amplitude level offset and gain values. An arithmetic logic unit combines these compensation values with the programmed values. The compensated values are then sent to test system registers that control pin resources, such as pin electronics of the semiconductor testing system.

Abstract: A novel test procedure is used to determine the optimum programmable charge pump levels for a flash memory array in a CPLD. According to the method of the invention, an automated tester steps through all combinations of charge pump codes and attempts to program the flash memory with each combination of voltage levels. For each combination, the results of the test (pass or fail) are logged and stored into a map or array. The center of a window of passing pump codes is taken as the starting reference point. The next step is to verify the actual voltage level associated with the pump code combination corresponding to the starting reference point. The reference pump code is loaded into the device and the corresponding flash memory cell voltage levels are measured. If the measured voltage level does not fall into the preferred range, the tester automatically adjusts the level towards the preferred range by adjusting the pump codes.

Abstract: Structures for saving states of memory cells in an FPGA while the FPGA is being configured are shown. Structures for saving flip flop states, lookup table configurations, and block RAM states are specifically described. Structures are described having (1) a SAVE STATE bit for saving the state of each flip flop, each lookup table RAM, and each block RAM. With these structures, each storage unit can be selectively restored. (2) a SAVE STATE bit for each row(column) of logic blocks in the FPGA. In such structures it is possible with a single SAVE STATE signal to selectively save or restore every memory element in the row, possibly including flip flops, lookup tables, and blocks of RAM. Several structures and methods for providing the SAVE STATE signal are also described.

Abstract: An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.

Abstract: A voltage regulator for a charge pump is provided with two input paths from a reference input voltage to a comparator, each path having a node between a capacitor pair. The two paths are alternately initialized and used to control the charge pump which generates a reference output voltage, so that the reference output voltage tracks the reference input voltage at all times. Each path has its own capacitor divider and switching circuitry to alternately connect the nodes between the respective pairs of capacitors to the comparator, which compares the nodes to a second voltage reference. Since the circuit is alternately initialized, any alterations to the voltage introduced at the nodes between each of the two capacitor pairs, are corrected to the proper level within a short time.

Abstract: An improved circuit tester allows for increased storage of test vectors in existing memory structures by noting where segments of test vectors repeat and storing such segments only once, then further utilizing memory space corresponding to otherwise unused test channels. Switching circuitry is included to selectively forward signals to and from a designated, multi-source conductor.

Abstract: A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

Abstract: An EPLD having improved routing and arithmetic function implementation characteristics. Cascade and carry logic in macrocells allows for rapid implementation of arithmetic functions without unnecessarily tying up device processing and interconnect resources or unnecessarily delaying processing.

Abstract: A method of providing placement information during design entry is described which includes the steps of indicating an element type in an instance, identifying a port list for a specific element in the instance, and providing embedded placement information regarding the specific element in the instance. In one embodiment, the embedded placement information includes a cell location, whereas in another embodiment, the embedded placement information includes a block location. This method eliminates the need for a separate file with placement information, thereby improving user efficiency and significantly minimizing user error.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution units may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction units in parallel, through appropriate decoding resources. A RISA instruction page table is used to detect when an instruction in the sequence has not been configured for the RISAs on chip.

Abstract: A method by which a two-dimensional array of logic elements may be interconnected such that they may be modeled as a three-dimensional array, while minimizing routing crossings. The result is an arrangement that is highly efficient for implementation in a silicon die. The preferred model may be extended to a three-dimensional torus where opposing faces of the array are considered to be adjacent. Routing flexibility is increased by increasing local interconnect while minimizing interconnect crossover.

Abstract: A six-input multiplexer is disclosed using only two transistors in the signal path from an input port to the output port. The multiplexer uses control signals that are not decoded. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A compact layout results when two multiplexers use common input signals.

Abstract: A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction unit in parallel, through appropriate decoding resources.

Abstract: For FPGAs and other logic devices using four-input function generators, several combinations of primitive functions are provided for mapping hardware descriptions of logic designs into the FPGAs or logic devices. Automatic tools using this library will reliably produce dense designs when implemented in coarse-grained architectures.

Abstract: A method and system for measuring programmed antifuse resistance in an FPGA without disturbing the antifuse resistance. The method includes estimating a plurality of subparts of the programming path connecting low and high programming voltage sources on the FPGA device, measuring the path as a whole, and subtracting the sum total of the subparts from the whole path measurement, thereby deriving the antifuse resistance. If the derived antifuse resistance is higher than desired, programming and measurement may be repeated to ensure device longevity and accurate timing for implemented designs.