Abstract: A method and structure for verifying interconnect structure of an FPGA device after programming. In a preferred embodiment, after programming, a single wire segment on each net of a layout is pulled down to a low reference voltage. Voltage levels on all wire segments of the device are then captured and shifted out of the device for comparison to the expected values. Low voltage levels on segments expected to remain high reveal short circuit flaws. High voltage levels on segments expected to remain low reveal open circuit flaws. The test is conducted simultaneously on a group of packed nets, wherein each group comprises a number of disjoint nets separated from one another by at least two MicroVia.TM. interconnects. A preferred packing method minimizes the number of net groups on a device for maximum test efficiency.

Abstract: A system for providing real time design feedback to a user of a data processing system for designing an electronic circuit includes a display system, a graphical, textual or mixed user input process which displays user input on the display system for designing an electronic circuit, and an implementation process with which generates an implementation of the electronic circuit in for example a field programmable gate array. Feedback is provided by monitoring the user input process to detect a change in the design of the electronic circuit. Upon detection of a change, information about the change is forwarded to the implementation process. The implementation process is executed as a background process to the user input process, in response to the change to produce implementation data on an incremental basis. Information about the implementation data is displayed on the display system as feedback to the user during the design process.

Abstract: A system and method for event-driven simulation of a circuit is disclosed. The system includes a simulation history of events and node values at various times throughout the simulation of the circuit. The system allows the user to access the simulation history during the simulation, make changes to the state of the circuit at any time recorded within the simulation history, and resume the simulation of the circuit automatically corrected for any changes.

Abstract: An integrated power supply and battery charger with interchangeable and collapsible plug capacity and interchangeable power input modules includes a casing, an electrical plug detachably mounted in the casing and including collapsible prongs, allowing the user to accommodate myriad combinations of power source configurations, electrical devices and rechargeable batteries therefore and to power and charge same in a safe and convenient manner. A cradle accommodates a battery to be charged. Releasable locking mechanisms are included to both engage the interchangeable electrical plug and battery and to lock the collapsible prong in the extended position. The locking mechanisms can be released by a user to allow the plug or battery to be moved to the detached position. A preferred form of electrical connection between a detachable plug and casing comprises a submerged pin and sleeve configuration to protect the user or passerby from electric shock.

Abstract: A latch may be formed as a two-part structure, one part for data input and one part for feeding back the data to form the latch. A clock signal controls whether data from a data input terminal will be forwarded to the output or whether the output signal will be provided as input and forwarded, thus forming the latch. A problem called the static ones hazard, namely registering a logical 0 when data input is logical 1, can occur with a latch of this logic structure when the circuit is entering the latch mode. In accordance with the invention, this static ones hazard is avoided by controlling trip points in the gates of the cell and input buffers of the cell so that the cell implements a make-before-break transition.

Abstract: An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.

Abstract: An electrical adapter plug insertable into cigarette lighter-type sockets of varying diameters. The plug features a flexible dimpled member integrally joined with the periphery of the plug to provide a variable outer plug diameter. An internal spring provides an outwardly biasing force to increase resistance against vibration and jarring and improve retention of the plug within the socket.

Abstract: A method and structure for verifying interconnect structure of an FPGA device after programming. In a preferred embodiment, after programming, a single wire segment on each net of a layout is pulled down to a low reference voltage. Voltage levels on all wire segments of the device are then captured and shifted out of the device for comparison to the expected values. Low voltage levels on segments expected to remain high reveal short circuit flaws. High voltage levels on segments expected to remain low reveal open circuit flaws.

Abstract: In an FPGA having registers which are part of a user's logic functions and a configuration memory which is read and written through an addressing structure, a register protect circuit controllably protects the contects of these user logic registers from being modified by signals from the user's logic, allows these registers to be written by a microprocessor through the configuration memory addressing structure, and allows both the user's registers and lines which provide combinational signals to be read by a microprocessor through the configuration memory addressing structure.