Abstract: In an ultra high voltage lateral DMOS-type device (UHV LDMOS device), a central pad that defines the drain region is surrounded by a racetrack-shaped source region with striations of alternating n-type and p-type material radiating outwardly from the pad to the source to provide for an adjustable snapback voltage.

Abstract: A method of performing wireless communications. The method receives at a receiving unit a sequence of data blocks from a transmitting unit. The method also identifies at the receiving unit a first number of invalid sequential data blocks in the sequence and a second number of valid sequential data blocks in the sequence. The method also communicates from the receiving unit a wireless message to the transmitting unit. The wireless message comprises a first field that specifies the first number and a second field that specifies the second number—the encoding of the first field is operable to specify a different maximum than an encoding of the second field.

Abstract: Provided is a method for manufacturing a semiconductor device. The method, in one embodiment, includes calibrating an inspection tool configured to obtain a measurement of a semiconductor feature, including: 1) providing a test structure comprising a substrate having a trench therein, and a post feature located over the substrate adjacent the trench. The post feature, in this embodiment, includes a second layer positioned over a first layer, wherein the first layer has a notch or bulge in a sidewall thereof; 2) finding a location of the notch or bulge relative to a different known point of the test structure using a probe of the inspection tool; and 3) calculating a dimension of the probe using the relative locations of the notch or bulge and the different known point.

Abstract: A full duplex transceiver has cancellation circuitry that includes an auxiliary receiver and an auxiliary transmitter. More specifically, an analog received signal that includes transmission signal leakage is provided to a low noise amplifier (LNA), which then provides its output to a main receiver and the auxiliary receiver. The auxiliary receiver includes a portion operable to convert the received signal from the analog domain to the digital domain. The auxiliary receiver additionally includes a cancellation processor that determines the transmission signal leakage and generates a signal based on the determined leakage. This signal generated by the auxiliary receiver is provided to the auxiliary transmitter, which converts the digital signal back to the analog domain and generates a cancellation signal. The analog cancellation signal is fed back and added to the received signal at the input of the LNA.

Abstract: The objective of this invention is to provide a type of photodiode and the method of manufacturing the photodiode characterized by the fact that it has a higher photoelectric conversion efficiency (sensitivity) than that in the prior art. PIN photodiode 100 has a p-type silicon substrate, p-type silicon layer 112, n-type silicon layer 114 formed on p-type silicon layer 112 and having a junction plane with silicon layer 112, n-type low-resistance silicon region 116 that is formed to a prescribed depth from the surface of silicon layer 114 and has an impurity concentration higher than that of silicon layer 114, silicon oxide film 120 formed on silicon region 116, and silicon nitride film 122 formed on silicon oxide film 120.

Abstract: A cable detector includes one or more peak detectors that detect when a termination impedance is missing from the output of a line driver. A peak detection signal is asserted when signals on a transmission line exceed a threshold level. A fault condition is asserted when the peak detection signal is asserted for a sufficient length of time to indicate that an actual fault is detected. The time period required for detecting a lost or missing line termination is longer than the time periods for any one of the pathological conditions to avoid a false positive detection. After the peak detection signal is de-asserted, the fault condition will be maintained until another sufficient length of time has expired without a peak detection.

Abstract: Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance.

Abstract: A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 ?m to about 35 ?m.

Abstract: A solar panel smart sensor system is disclosed. The sensor system permits solar power system owners and operators to monitor the voltage of individual panels in a solar array. The system uses a low wire-count bus in which the order of sensors on the bus is automatically determined. A novel technique is used to measure DC voltages of panels that may be floating hundreds of volts above ground. Bypass diodes are monitored to detect lost power generation capacity.

Abstract: A method includes receiving a control signal associated with a load, where the control signal is to cause a load change from a perspective of a switching-mode power supply. The method also includes causing the power supply to adjust a current through an inductor of the power supply in response to the control signal. The method further includes delaying delivery of the control signal in order to delay a time of the load change, where the current through the inductor increases during the delay. The control signal could include a request to turn on one or more LEDs. The load could include a current regulator. The method could further include providing the request to the current regulator after the delay, such as after the current through the inductor reaches a specified level. Voltage spikes and audible noise in a capacitor coupled to an output of the power supply can be minimized.

Abstract: An apparatus includes pulse width modulation (PWM) circuitry configured to generate a PWM signal based on a feedback voltage associated with current flowing through a load, such as one or more light emitting diodes (LEDs). The apparatus also includes a power switch configured to control the current flowing through the load on the PWM signal. The apparatus further includes averaging circuitry configured to provide an average of the feedback voltage to the PWM circuitry. The averaging circuitry is may be configured to provide the feedback voltage to the PWM circuitry during a first phase of operation and to provide the average of the feedback voltage to the PWM circuitry during a second phase of operation. The average of the feedback voltage may be referenced to a reference voltage received by an error amplifier in the PWM circuitry during both the first and second phases of operation.

Abstract: Various semiconductor devices can be formed at the end of a common fabrication process, thereby significantly improving manufacturing flexibility, by selectively wiring bonding different CMOS circuits to different MEMS, which are formed on the same semiconductor die. A semiconductor device that has a number of CMOS circuits and a number of MEMS is formed on the same semiconductor wafer in adjacent regions on the wafer, and then diced such that the CMOS circuits and the MEMS are formed on the same die. After dicing, different CMOS circuits and different MEMS can be selectively connected during the wire bonding step to form the different semiconductor devices.

Abstract: A circuit for reducing and offsetting the voltage swing of a differential pre-drive circuit. The circuit includes a first H-bridge of transistors receiving a differential pair of input signals. A swing resister is coupled to the H-bridge for reducing a voltage swing of the differential pair of input signals. The reduced swing is generated as a differential pair of output signals. Also, the differential pre-drive circuit includes an offset resistor that is coupled to the H-bridge. The offset resistor acts to offset the differential pair of output signals. As such, the differential pair of output signals having reduced swing and offset as applied to gates of output transistors in an output stage allow the output transistors to remain in the saturation operating state.

Abstract: A system and method for monitoring performance of one or more solar panels in a photovoltaic array. The system and method includes a number of sensors are configured to measure an output of individual solar panels. A telemetry gateway collects data from the sensors and transmits the collected data to a monitoring system. The monitoring system includes an event signature recognizer; a trend analyzer; and a symmetry analyzer. The monitoring system detects events, trends and solar panel array asymmetry. Additionally, the monitoring system displays realtime graphs, proposed corrective actions, and alerts via a user interface.

Abstract: An apparatus includes at least one filter configured to filter a reference voltage to generate a filtered reference voltage. The apparatus also includes an amplifier configured to amplify a difference between the filtered reference voltage and a feedback voltage to generate a drive signal. The apparatus further includes a first transistor configured to generate an output voltage based on the drive signal, where the feedback voltage is based on the output voltage. The apparatus also includes a second transistor configured to generate a first bias current for the amplifier based on the drive signal. In addition, the apparatus includes a voltage-to-current converter configured to generate a second bias current for the amplifier based on the reference voltage and the feedback voltage. The second transistor can generate higher first bias currents during higher load currents, and the voltage-to-current converter can generate higher second bias currents during faster load current variations.

Abstract: A method includes receiving an input voltage at a voltage regulator and generating an output voltage using the voltage regulator, which includes an inductor. The method also includes controlling a current through the inductor using a current limit reference and modulating the current limit reference based on the input voltage and the output voltage. Modulating the current limit reference could include modulating a reference current based on a product of first and second input currents. The first input current may be based on the output voltage, and the second input current may be based on a difference between the output and input voltages. The voltage regulator may operate in a pulse frequency mode associated with a repetition rate. The repetition rate and a percentage ripple associated with the output voltage may be substantially constant over variations in the input voltage and variations in the output voltage.

Abstract: A method of manufacturing a memory cell 200. The method comprises forming a memory stack 215. Forming the memory stack includes pre-treating an insulating layer 210 in a substantially ammonia atmosphere for a period of more than 5 minutes to thereby form a pre-treated insulating layer 310. Forming the memory stack also includes depositing a silicon nitride layer on the pre-treated insulating layer.

Abstract: An electrostatic discharge (ESD) protection circuit includes a control circuit configured to generate a signal indicating whether an input voltage on an input/output pad is excessive. The protection circuit also includes a voltage divider configured to receive the signal from the control circuit and to divide the input voltage to produce a divided voltage. The protection circuit further includes an inverter chain having multiple inverters, where a first inverter is configured to receive the divided voltage and at least two inverters are configured to generate transistor control signals. In addition, the protection circuit includes a plurality of transistors configured to receive the transistor control signals and, when the input voltage is excessive, to prevent the input voltage from being provided to a protected circuit.

Abstract: In accordance with the invention, there are semiconductor devices and methods of making semiconductor devices and holes. The method of making a semiconductor device can comprise forming a photoresist layer over a surface of a wafer, wherein the wafer comprises an edge that has a substantially rounded profile, an array of dies, and at least one edge die. The method can also comprise dividing a shot area into a plurality of shot portions and assigning a blind ID to each of the plurality of shot portions. The method can further comprise identifying one or more edge shot portions on the edge of the wafer for additional exposure; and exposing one or more times identified one or more edge shot portions on the edge of the wafer and blocking non-identified one or more non-edge shot portions.

Abstract: A system for calibrating operation of integrated differential signal receiver circuitry mounted on a substrate and coupled via surface conductors to edge mounted interface electrodes in which compensation is provided for variances among the resistances of the surface conductors.