Abstract: A novel and useful range extension and in-band noise mitigation mechanism that uses conventional CRC error detection codes to correct single and multiple bit errors in packets received over a communications link. The CRC error correction mechanism of the invention is particularly suitable for use with communication protocols with weak error correction capabilities. The mechanism uses the linearity property of the CRC calculation to detect the existence of errors in the received packet. The entire received packet is searched for single bit errors and are corrected in a single cycle. If no single bit errors are found, the mechanism then searches for multiple bit errors. Packet retransmissions are used to detect and mark the location of multiple bit errors. Multiple bit errors are corrected by trying a plurality of hypotheses of single bit error corrections. Each hypotheses pattern is investigated to find matching CRC patterns for correction using the single bit, single cycle CRC error correction method.

Abstract: A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation.

Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26?). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26?), to inhibit the diffusion of dopant from the buried collector region (26?) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26?) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26?) can diffuse upward to meet the contact (33).

Abstract: A near field communication (NFC) transceiver contains a transmitter portion to generate a transmit wireless signal, and a receiver portion to receive and process a receive wireless signal. The circuit further contains a shunt capacitor, a switch, and an antenna interface to couple the transmitter portion and the receiver portion to an antenna designed to communicate with external antennas by inductive coupling. The switch couples the shunt capacitor in parallel with the antenna in one operational mode, and decouples the shunt capacitor from the antenna in another operational mode. Transmit and receive performance of the NFC transceiver are enhanced as a result.

Abstract: A base station transmitter for use with an orthogonal frequency division multiplexing (OFDM) communications system, a method of dynamically allocating OFDM symbols needed for a physical downlink control channel (PDCCH) in a downlink sub-frame from a base station and a user equipment (UE) receiver for use with the OFDM communications system. In one embodiment, the UE receiver includes: (1) a receive unit configured to receive a downlink signal, the signal having groups of control information and (2) a processing unit configured to extract from the groups of control information a number of OFDM symbols needed for PDCCH in a sub-frame of the downlink signal.

Abstract: A digital phase lock loop circuit, where under certain conditions the phase error is derived from phase comparison between a reference clock edge and the next oscillator clock edge rather than a feedback clock edge. This technique can be used to significantly reduce digital phase lock loop circuit power by disabling feedback divider and sync FF once initial frequency lock is established, provided phase jitter of digital phase lock loop circuit is low enough so that there is no cycle slip. This technique can also be used to multiply the effective reference clock frequency of digital phase lock loop circuits to increases the loop bandwidth, thus reducing the phase noise. Both the applications of this technique can be combined in some circuits.

Abstract: A novel and useful apparatus for and method of integrating the advanced audio distribution profile (A2DP) audio codec into a Bluetooth controller for audio streaming applications. The mechanism functions to break the prior art Bluetooth protocol stack by integrating a profile packet composer into the controller. The profile/stack control signaling is performed by the host while the profile data packet composer is implemented in the controller. The integrated data packet composer does not break the data path and flow control over the standard HCI. Further, the integrated packet composer allows the controller to open a dedicated data interface for specific applications (e.g., PCM/I2S for audio data).

Abstract: One aspect of the invention includes a communication system that includes a tone generator configured to generate a first tone, a second tone, and a third tone. The third tone can have a frequency that is a harmonic product of at least one of the frequencies of the first and second tones. A transmitter that includes a predistortion system transmits a test signal comprising the first, second, and third tones. A receiver that is communicatively coupled to the transmitter receives and processes a received test signal corresponding to the test signal. The system further includes a controller that generates a set of correction coefficients based on a measured interaction of the third tone with a non-linear signal component in the received test signal. The set of correction coefficients can be provided to the predistortion system for substantially linearizing communication signals transmitted from the transmitter.

Abstract: A circuit for use with an amplification circuit having a predistortion datapath portion, a power amplifier portion and a gain portion. The predistortion datapath portion can output a predistorted signal based on the input signal. The power amplifier portion can output an amplified signal based on the predistorted signal. The gain portion can output a gain output signal based on the amplified signal. The circuit comprises a digital predistortion adaptation portion and a combiner. The digital predistortion adaptation portion can output a predistortion adaptation portion output signal. The combiner can output an error signal. The predistortion adaptation portion output signal is based on the input signal, the gain output signal and the error signal. The error signal is based on the difference between the predistorted signal and the predistortion adaptation portion output signal.

Abstract: A three terminal bi-directional laterally diffused metal oxide semiconductor (LDMOS) transistor which includes two uni-directional LDMOS transistors in series sharing a common drain node, and configured such that source nodes of the uni-directional LDMOS transistors serve as source and drain terminals of the bi-directional LDMOS transistor. The source is shorted to the backgate of each LDMOS transistor. The gate node of each LDMOS transistor is clamped to its respective source node to prevent source-gate breakdown, and the gate terminal of the bi-directional LDMOS transistor is connected to the gate nodes of the constituent uni-directional LDMOS transistors through blocking diodes. The common drain is a deep n-well which isolates the two p-type backgate regions. The gate node clamp can be a pair of back-to-back zener diodes, or a pair of self biased MOS transistors connected source-to-source in series.

Abstract: A Sigma-Delta Modulator (SDM) has a summing junction that receives an input signal and a feedback signal, a multi-level analog-to-digital converter (ADC) that receives the SDM input signal and generates an ADC output, a first analog switch that receives the ADC output and generates a plurality of reference voltages, a second analog switch generating the feedback signal, where the feedback signal is selected from one of the reference voltages.

Abstract: Methods, apparatus, and articles of manufacture are described for improving distortion performance and for direct current offset cancellation in receivers. In one example, a method of improving distortion in a receiver includes determining a direct current (DC) amplitude of an offset signal, generating the offset signal, and providing the offset signal to an output of a mixer to improve the distortion performance of the mixer.

Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.

Abstract: Methods and mobile devices are provided for asymmetric independent processing of audio streams in a system on a chip (SOC). More specifically, independent audio paths are provided for processors performing audio processing on the SOC and mixing of decoded audio samples from the processors is performed digitally on the SOC by a hardware digital mixer.

Abstract: In accordance with embodiments, a method for configuring an electronic device during a power-on sequence includes sampling a boot pin state multiple times. The method also includes storing a value corresponding to each sampled boot pin state, wherein the stored values comprise one of four different states for a single boot pin.

Abstract: A variable gain amplifier may include a master amplifier that may be configured to generate a first current and a diode coupled with the master amplifier so that the first current passes through the diode which, when the first current is passing through the diode, generates a diode voltage signal. According to embodiments, an error amplifier may include a first input configured to receive a gain control voltage signal and a second input configured to receive the diode voltage signal. The output of the error amplifier may provide a feedback signal. The amplifier may include a circuit configured to generate at least one voltage control signal based on the feedback signal and a slave amplifier configured to adjust a gain amount based on the at least one voltage control signal.

Abstract: An input current channel device is described. This device comprises a first terminal for receiving a reference signal; a second terminal for receiving a first target signal; a pass through device coupled to the first terminal, the pass through device operative for transmitting a delayed reference signal in response to receiving the reference signal; a first combination logic device coupled to the first terminal and the second terminal, the first combination logic device operative for transmitting a first combination logic signal in response to receiving the reference signal and the first target signal; a selection device coupled for receiving the delayed reference signal, the first combination logic signal, and a first synchronization signal, the selection device operative for selectively transmitting a second synchronization signal, and wherein selectively transmitting the second synchronization signal reduces skew between the reference channel and the first target channel.

Abstract: A mechanical polishing apparatus includes a polishing pad, at least one carrier head positioned over and off center relative to the polishing pad and configured for holding at least one substrate against the polishing pad within a first annular region of the polishing pad when the polishing pad is rotating. At least one conditioning head is positionable over and off center relative the polishing pad at a plurality of first positions and configured for applying a contacting surface of at least one conditioning pad against the polishing pad when the polishing pad is rotating, where the conditioning pad is applied to a second annular region of the polishing pad and moves between the plurality of first positions. In the apparatus, the diameter of the conditioning pad?a difference between a radius of the polishing pad and a width of the first annular region.

Abstract: An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.

Abstract: An integrated circuit includes common gate FinFET and split gate FinFET devices formed from different height fins at a semiconductor surface of a substrate. A patterned layer of gate electrode material formed over sides and unconnected over the tops of the taller fins defines respective gate electrodes for first and second paired transistors. The patterned layer of gate electrode material formed over the sides and connected over tops of the shorter fins defines common gate electrodes for transistors. In one embodiment, the common gate devices are used for cross-coupled inverters of a memory cell core storage element and the split gate devices are used for pass gates, with the gate electrodes coupled to wordlines and common source/drains coupled to bitline/complementary bitline and core element storage/complementary storage nodes.