Abstract: A dynamic logic hold time latch (20). The latch comprises a first phase circuit (12?) operable in a precharge phase and an evaluate phase and a second phase circuit (22) operable in a precharge phase and an evaluate phase. The precharge phase and the evaluate phase of the second phase circuit are out of phase with respect to the precharge phase and the evaluate phase of the first phase circuit. The first phase circuit comprises a precharge node (12?PN) to be precharged to a precharge voltage during the precharge phase of the first phase circuit and operable to be discharged during the evaluate phase of the first phase circuit. The first phase circuit also comprises an output (12?OUT) for providing a signal in response to a state at the precharge node of the first phase circuit.

Abstract: The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential input coupled to a differential output of the pre-amplifier; and a replica comparator coupled to a common mode node of the pre-amplifier for adjusting a common mode of the pre-amplifier. The replica comparator provides a trip-point reference to set the output common mode of the pre-amplifier. This sets the output common mode of the pre-amplifier to the most sensitive region of the re-generated comparator.

Abstract: A crossbar circuit (30, 40, 50, 60, 70, 80, 90, 100) having programmable repeater structures adapted to allow configuration of the crossbar with inputs at multiple sides of the crossbar die. A plurality of repeaters (62) are arranged in different repeater structures such that the repeater arrangement can be connected to inputs at different locations as a function of the corresponding input as it is physically positioned around the periphery of the crossbar. A pseudo code is provided allowing the repeater structures to be custom configured to corresponding inputs as a function of the desired crossbar as it is designed to be utilized in a particular large integrated circuit, such as a VLSI chip.

Abstract: The frequency doubling circuit and method provides an output signal with stable frequency and a 50% duty cycle. The frequency of the output signal is two times a frequency of the input signal. The circuit only requires four comparators, eight small capacitors, and some switches and transistors for frequency doubling applications. With the help of feedforward structure, the circuit has an almost-instantaneous response. The performance of the provided frequency doubling circuit and method is independent of the frequency and duty cycle of input signal, power supply voltage, temperature, and process variations.

Abstract: According to one embodiment of the invention, a method for predicting burn-in conditions includes identifying a baseline IDDQ, a baseline temperature, and a baseline IDDQ current density based on a plurality of existing burn-in data for one or more existing devices, determining a theoretical IDDQ current density for a device, determining a ratio of the theoretical IDDQ current density to the baseline IDDQ current density, determining a theoretical process metric for the device at the baseline temperature based on the ratio and the baseline IDDQ, measuring a process metric for an actual device, comparing the process metric for the actual device and the theoretical process metric for the device, and determining an actual burn-in temperature for the actual device based on the comparison.

Abstract: An embodiment of a ultra low-power data retention latch circuit involves a slave latch SL that concurrently latches the same data that is loaded into a main circuit (such as a main latch ML) during normal operation. When the circuit enters a low power (data retention) mode, power (VCC) to the main latch ML is removed and the slave latch SL retains the most recent data (retained data SA, SA-). When power is being restored to the main latch ML, the slave latch's retained data SA, SA- is quickly restored to the main latch ML through what constitute Set and Reset inputs SAR, SAR- of the ML. This arrangement ensures that data restoration is much quicker than conventional arrangements that require the output data path DATA- to be stabilized before power is re-applied to the main latch. Further, there is no need to wait for power to the ML to be stable before restoring data from the SL to the ML, providing an increase in data restoration speed over conventional data retention latches.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

Abstract: A circuit for reducing standby leakage in a memory unit contains a capacitive divider coupled to the memory unit so as to generate a voltage across the memory unit, which is adequate to retain memory values during one of a sleep state and a standby state. An inductive circuit for reducing standby leakage in a memory unit includes an inductive divider coupled to the memory unit so as to generate a voltage across the memory unit, which is adequate to retain memory values during one of a sleep state and a standby state.

Abstract: Generating an oscillating signal according to a control current includes receiving a control current corresponding to an oscillation frequency. A first differential signal and a second differential signal are generated by switching a first load according to the control current to yield the first differential signal, and switching a second load according to the control current to yield the second differential signal. The first load operates in opposition to the second load.

Abstract: A current limit circuit regulates the current flow through a power switch 90 by measuring the current through the switch 90 and comparing it to a reference voltage VREF that represents the limit current. When the current through the power switch 90 is greater than the limit current, the current in the power switch 90 is pulled lower by a driver circuit 92 which controls the power switch 90. By using a current limit reference voltage that has two levels, the power switch 90 has two current limit thresholds. Using a comparator 94 to compare the input voltage of the power switch 90 to the output voltage of the power switch 90, an output signal is generated to control the current limit threshold. When the input voltage and output voltage has a large differential voltage, a lower current limit threshold voltage is selected. When the input voltage and output voltage has a small differential voltage, an upper limit threshold voltage is selected.

Abstract: A sigma delta class D device that uses a low pass filter to smooth the output waveform and eliminate high frequency switching noise from the feedback value includes: a first summing node having a positive input coupled to a signal input node; a second summing node having a first positive input coupled to an output of the first summing node and having an output coupled to a signal output node; a low pass filter having an input coupled to the output of the second summing node; an analog to digital converter having an input coupled to an output of the low pass filter; a third summing node having a positive input node coupled to an output of the analog to digital converter and a negative input node coupled to the output of the first summing node; and a feedback device coupled between an output of the third summing node and a negative input of the first summing node.

Abstract: An linear optical sensor charged-coupled topology using single-stage inverting charge-coupled amplifier driving an analog-to-digital converter which uses the converter full-scale reference as a precharge level. Since an offset in the range of 100–200 mV is introduced in the charge amplifier, a corresponding offset is also introduced into the ADC to allow the amplifier to more quickly drive the amplifier output to a low level. The converter offset is proportional to the converter reference to ensure that it is controlled and tracks the reference.

Abstract: An apparatus includes a voltage regulator operable to regulate a supply voltage to an on-chip module having an operational current, draw a supply current, and supply the operation current to the on-chip module. The supply current drawn by the voltage regulator is proportional to the operating current of the on-chip module.

Abstract: The objective is to provide a sampling/holding circuit that can operate at high speed and low power consumption. The sampling/holding circuit has multiple sampling units 2-1˜k. Each sampling unit has input terminals 1-1˜k and output terminals 3-1˜k. The values received at the input terminals are sampled, and the sample values are accumulated. Also, the accumulated sample values are generated at output terminals 3-1˜k. One holding unit 6 has an input terminal 5 and an output terminal 7, which are shared by the multiple sampling units. By multiplexing the outputs of the multiple sampling units, multiplexing unit 4 connects any output to the input of holding unit 6. Holding unit 6 holds the sample value and generates it at output 7.

Abstract: The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction component 302 performs duty cycle corrections on a pair of differential sinusoidal signals according to a pair of adjustment signals and, as a result, generates a differential pair of square wave signals. A cross coupled buffer 306 buffers the differential pair of square wave signals and provides the buffered signals to a feedback circuit 304 that measures duty cycles of the signals and generates the pair of adjustment signals accordingly. The buffer 306 can also remove skew from the signals. In a transmitter 102, the buffered signals are also generally provided to a multiplexer 112 or encoder and in a receiver 106, the buffered signals are also generally provided to a sampling component 122.

Abstract: A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates a self-timed strobe signal along with other control signals that are used to perform a subsequent memory access in a single clock cycle, thereby doubling memory access bandwidth.

Abstract: Reducing the time required to measure constraint parameters (setup time, hold time and pulse width) of components in integrated circuits. For example, the delay of propagation of a signal between an input node and an intermediate node of a component are measured. An approximate range of possible values is formulated, and a search (by applying signals assuming one of the values in the approximate range and examining the output signal(s)) is conducted within the range to determine the value of the constraint parameters.

Abstract: The asymmetric digital subscriber line receive channel includes: first and second external resistors 20 and 22 coupled to a telephone line 24 and 26; a coarse programmable gain amplifier CPGA formed in a low voltage process having inputs coupled to the first and second external resistors 20 and 22; and a fine programmable gain amplifier PGA1 coupled to an output of the coarse programmable gain amplifier CPGA, and having a very fine gain trim adjustment to compensate for a mismatch between the external resistors 20 and 22 and the coarse programmable gain amplifier CPGA.

Abstract: A low drop-out voltage regulator uses a voltage subtractor circuit 36 to form a power supply rejection boost circuit. The voltage subtractor 36 is inserted between the pass element 20 and the amplifier 26 of the low drop-out regulator. The voltage regulator circuit includes a pass element 20 coupled between an input node and an output node; a voltage feedback circuit 28 and 30 coupled to the output node Vo; an amplifier 26 having an input coupled to the voltage feedback circuit; and a voltage subtractor 36 having a control node coupled to an output of the amplifier 26, an output coupled to a control node of the pass element 20, and an input coupled to the input node. The boost circuit improves supply noise rejection performance significantly without adding much complexity to the regulator system. The boost circuit is simple and consumes negligible silicon area and power.