Abstract: A voltage boosting circuit for a semiconductor memory device has a clock generator for supplying a chip master clock determining an active state and a stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of the chip master clock is generated, and for generating a latch control signal a second delay time after the first state of the chip master clock is generated. A boosting voltage detector responds to the detector control signal and the latch control signal to generate a detecting signal indicative of a current state of a boosting voltage potential. First and second boosting voltage generators generate the boosting voltage potential, respectively operating in the stand-by state and active state in accordance with the detecting signal and delayed chip master clock signal.

Abstract: A projection method uses a modified illumination method for a lithography process of semiconductor device, and a projection system and mask use the projection method. An object is exposed by removing the vertical incident component of light passed through a condenser lens. Zero-order diffracted light interferes destructively and the oblique component of -/+ first-order diffracted light, interferes constructively. The obliquely incident component light illuminates a mask having a pattern formed thereon. The vertical incident component of the light is removed by a phase difference of light due to a grating mask or a grating pattern formed on the back surface of the conventional mask. The resolution of a lithography process is improved due to the increased contrast, and the depth of focus is also increased. Thus, patterns for 64 Mb DRAMs can be formed using a conventional projection exposure system.

Abstract: Alternative methods for detecting a short-circuit between signal lines in an electrically erasable and programmable nonvolatile semiconductor memory device use circuitry for detecting short-circuited signal lines. One method includes the steps of: floating first and second signal lines in response to another external input; simultaneously forming an electrical path between the first and second signal lines and each test pad; and determining whether a current path is formed between the test pads, for detecting any short-circuit between the first and second signal lines. Another method includes the steps of: floating the first and second signal lines in response to another external input; simultaneously forming the electrical path between the first signal line and the test pad while discharging the second signal line to the reference potential; and determining whether a current path is formed from the test pad to the reference potential, for detecting any short-circuit between the first and second signal lines.

Abstract: A Huffman decoder includes a first latch for storing the current variable-length-encoded data, a second latch for storing the previous variable-length-encoded data, a single decoder for receiving the word size and outputting a selection signal, a data requirement signal generator for generating a data requirement signal when the added word size is over a predetermined size after summing the word sizes, a multiplexer for receiving the outputs of the first and second latches to select a predetermined bit according to the selection signal, a data rotator for cyclic-shifting the output of the multiplexer according to the word size to form a reconstructed data and outputting the reconstructed data, an addressing portion for comparing the reconstructed data with a predetermined value and decoding the data, and a memory for storing the size of the variable-length-encoded word and the fixed-length code corresponding thereto which are output according to the output of the addressing portion.

Abstract: A decoder uses look-up table memory for variable-length coding (such as Huffman coding) that comprises concatenated variable-length codes, most species of which codes can each be analyzed as being composed of a pointer subcode of variable bit-length and a target subcode of fixed bit-length, the target subcodes being relatively efficiently encoded and the pointer subcodes being relatively inefficiently encoded. The memory stores not only decoding results, but the bit-lengths of the codes generating those results. The bit-lengths of the concatenated codes are accumulated and the accumulation result in modular arithmetic is supplied to as shift control signal to a data shifter. The data shifter positions each successive one of the concatenated codes within a window so the leadmost bit of the code is positioned at the edge of the window. The pointer subcodes are decoded, applied to address lines of the memory, and used to select target subcodes to an address decoder.

Abstract: A line sync detector for a digital television receiver receives digital television data including line synchronization code groups of four symbols having successive values of +S, -S, -S and +S at the beginning of each data line, S being a prescribed sample level. A first delay line has an input tap to which the digital television data are supplied, an output tap, first and second intermediate taps, a first symbol latch having an input connection from the input tap and having an output connection to the first intermediate tap, a second symbol latch having an input connection from the first intermediate tap and having an output connection to the second intermediate tap, and a third symbol latch having an input connection from the second intermediate tap and having an output connection to the output tap. The signals at the input tap, the first and second intermediate taps and the output tap of the first delay line are combined in 1:(-1):(-1):1 ratio to generate a combined response.

Abstract: A reproduction error correction circuit for a video reproduction system includes a line-storage memory for temporarily storing composite video signal samples, which memory is operated to provide both for time-base correction and for drop-out compensation. The memory is cyclically supplied sequential write addresses descriptive of pixel locations along a horizontal scan line, generated at a rate that tracks any jitter in the input video signal selectively used for writing over the previous contents of the memory. The memory is cyclically supplied sequential read addresses offset 1/2 scan line from the write addresses, generated at a stable rate equal to an average over several scan lines of the rate at which write addresses are generated. This provides for time-base error correction. When a drop-out is detected, overwriting of video signal samples already stored in the single line-storage memory is prohibited.

Abstract: An automatic frequency control apparatus includes a sampling portion for sampling the signal transmitted according to a phase-shift keying method, a phase difference detector for detecting the phase difference between the currently sampled signal and the immediately preceding sampled signal, and a phase bin comparator for determining which of a number of reference phases the phase of the transmitted signal is closest to, using a quantization characteristic of phase during transmission. The frequency offset generated by the distance between the frequency of a carrier wave and the local oscillation frequency of a receiver, or by the Doppler shift, in a MPSK communication method is determined as the phase difference between the detected phase difference information and the determined reference phase information. The apparatus can be used for the automatic frequency control of a modem using any type of MPSK modulation.

Abstract: A video tape includes a plurality of parallel slant tracks formed therein. Each track includes a plurality of successively recorded sync blocks. In each sync block, a respective portion of a first digital signal recorded therein represents a predetermined portion of an input image with relatively low resolution, and a respective portion of a second digital signal recorded therein represents substantially the same predetermined portion of the input image with relatively high resolution. Successive sync blocks include consecutive portions of the first digital signal, which portions correspond to spatially adjacent portions of the input image. Preferably, each sync block includes a fixed number of bits of the first digital signal, which is decodable without reference to any image coded signal from other sync blocks.

Abstract: A clock generating circuit generates 2n clocks (where n is a positive integer number) each having 1/2n frequency of a maximum baud rate of data bit-stream input and a phase difference of .pi./n between successive phases thereof, and simultaneously shifts the phases on the clocks ahead or behind until the phases between the clocks and corresponding data bits of the data bit-stream input are locked in quadrature, by comparing the phase of the clock with those of data bit-stream input and adjusting the phases of the clocks.

Abstract: A hard disk drive mounting assembly for a computer comprises a hard disk drive case held in the computer body by pins oppositely protruding from respective lower portions of the exterior surfaces of a pair of opposed sides of the hard disk drive case, having rails on the interior surfaces of those opposed sides, and having apertures in those opposed sides into which rail hooks can be inserted. The hard disk drive case can be tipped open or closed by turning around the pins as aligned separated axles. The had disk drive case is held closed by spring catches that engage notches in the computer body. The hard disk drive has slide members on its both sides and has rail hooks at predetermined positions on the sliding members for engaging the apertures in the opposed sides of the hard disk drive case. The hard disk drive mounting assembly utilizes the space of the computer body efficiently and permits mounting or removing a hard disk from the computer without any special implement.

Abstract: A binary counter or binary-coded-arithmetic counter uses local look-ahead to speed up ripple carry propagation. A succession of counter stages therein can be identified by respective consecutive ordinal numbers assigned in accordance with the order of carry propagation. Each counter stage receives a respective carry input and supplies a respective output signal, and each counter stage identified by even number supplies a respective complemented output signal. Each counter stage identified by odd number has a respective carry generation circuit for supplying a respective carry output signal which includes a NAND gate responsive to carry input to that counter stage and responsive to output signal from that counter stage, carry input for the next counter stage being supplied in response to the NAND gate response.

Abstract: A method for manufacturing a semiconductor device, e.g.

Abstract: A method of arranging column decoders in a video RAM, including the steps of arranging a memory cell array into a plurality of memory sub-cell arrays, and positioning a column decoder to one side of each memory sub-cell array between the memory sub-cell array and centrally located peripheral circuits including a predecoder. The column decoder includes a RAM column decoder section and a SAM column decoder section.

Abstract: In a television system including a source of an intermediate frequency (IF) signal, which signal includes an IF picture carrier amplitude modulated with video information, synchronous demodulator means responds to the IF signal, for providing an in-phase first output video signal that has both luminance and chrominance components, and for providing a quadrature-phase second output video signal that has a chrominance component but substantially no luminance component. Chroma circuitry is responsive to the quadrature-phase second output video signal for generating first and second color-difference signals.

Abstract: A high-performance television receiver synchronously detects the picture IF signal. A synchronous impulse noise in the IF signal generates either positive-going noise or negative-going noise in the video signal supplied from a synchronous video detector, which noise is subsequently replaced by a value of video signal occurring previous to the impulse noise in the following manner. The video signal contaminated with impulse noise is supplied as input signal both to an impulse noise detector and to a delay line. The output signal from the delay line, delayed by about 240 ns, is supplied as the signal for tracking by a track-and-hold circuit. The detected impulse noise signal is used to actuate the hold condition in the track-and-hold circuit. By stretching the pulse from the impulse noise detector for the 600-800 ns duration overlapping the duration of most impulse noise, the track-and-hold circuit replaces most impulse noise with previously stored values of the delayed video signal.

Abstract: A projection method uses a modified illumination method for a lithography process of semiconductor device, and a projection system and mask use the projection method. An object is exposed by removing the vertical incident component of light passed through a condenser lens. Zero-order diffracted light interferes destructively and the oblique component of .-+. first-order diffracted light, interferes constructively. The obliquely incident component light illuminates a mask having a pattern formed thereon. The vertical incident component of the light is removed by a phase difference of light due to a grating mask or a grating pattern formed on the back surface of the conventional mask. The resolution of a lithography process is improved due to the increased contrast, and the depth of focus is also increased. Thus, patterns for 64 Mb DRAMs can be formed using a conventional projection exposure system.

Abstract: In a communication system serving a plurality of transmitter-receivers, high capacity is achieved by asynchronous contention access of relatively short reservation request packets, which if successfully transmitted result in the scheduled, noncontention transmission of relatively long message data packets. In a first embodiment, the reservation request packets bear information relating to the duration of the message data packets, so that appropriate message data transmission time may be scheduled. Unsuccessful or colliding reservation request packets are retransmitted. In a second embodiment, the reservation requests packets do not include duration information, and the message data packets have fixed duration. In the second embodiment, collision resolution techniques allow the message data scheduling without retransmission of some colliding reservation request packets.

Abstract: A radio frequency transmitter simultaneously transmits both a local oscillator frequency and that frequency modulated by an information content signal. A receiver receives a carrier wave that is at the opposite edge of a channel from that of the local oscillator. The transmitted and received information signals can be of opposite type sidebands.

Abstract: A method for forming a silicon dioxide layer on a silicon island on an insulating substrate includes the steps of initially providing an insulating substrate having a major surface on which a silicon island is disposed. The surface of the silicon island is then thermally oxidized and a silicon layer is deposited on the oxidized island and the portion of the substrate surface adjacent to the island. This entire silicon layer is then oxidized and a conductive polycrystalline silicon electrode is deposited thereon.