Abstract: A decoder circuit for fully decoding N input variables includes 2.sup.N logic gates arranged into 2.sup.N-1 pairs of gates, with each gate having N inputs, and one output. The decoder also includes (N-1) inverters for producing the complements of N-1 of the N input variables whereby the (N-1) input variables and their complements are arranged into 2.sup.(N-1) different combinations of (N-1) signals for generating a different combination of (N-1) signals per pair of logic gates. (N-1) inputs of each of the two gates forming a pair of gates are interconnected to receive the same N-1 input signals forming one of the 2.sup.N-1 combinations. The Nth input variable is applied to the Nth input of one gate from each pair of gates and the output of the one gate from each pair is connected to the Nth input of the other gate with which it is paired.

Abstract: A CCD storage register for storing an area array of picture elements in a solid-state imager comprises a plurality of charge transfer channels in a parallel array. Charge transfer stages in those channels have corresponding charge storage sites facilitating charge transfer from each charge transfer stage to its corresponding charge storage site. Provisions are also made for charge transfer from each charge storage site back to its corresponding charge transfer stage or to a subsequent charge transfer stage. Such charge transfer schemes allows shift and add procedures to be carried forward in the CCD storage register. The shift and add capability allows time-delay-integration procedures and true line interlacing procedures, as examples, to be carried forward in the CCD storage register.

Abstract: A silicon-on-insulator (SOI) device is fabricated by forming at least one island of semiconductor material on a surface of an insulating material. Silicon is then formed on the areas which surround the at least one island. The silicon is oxidized to form silicon dioxide regions which surround the at least one island.

Abstract: An SOS integrated circuit includes a plurality of spaced islands of single-crystalline silicon on a surface of a sapphire substrate. A conformal layer of silicon oxide is on the surface of the sapphire substrate between the islands and extends along a portion of the side surfaces of the islands. A layer of polycrystalline silicon is over the silicon oxide layer and extends over the side surface and at least a portion of the top surface of the islands. A separate field-effect transistor is on each island and includes source and drain regions spaced by a channel region and a channel dielectric layer over the channel region. The polycrystalline silicon layer may extend over the channel dielectric to serve as the gate of the transistor. The method of making the circuit includes depositing the silicon oxide layer over the sapphire substrate surface and the islands, and applying a layer of a negative photoresist over the silicon oxide layer.

Abstract: A method and apparatus for determining the location and size of structural defects in a body of solid material, particularly regions of thermoplastic deformation in semiconductor wafers. An acoustical focused beam generated by an ultrasonic transducer, having a pulsed frequency of at least 75 MHZ, is transmitted through the body to provide an attenuated signal pattern which manifests structural defects, such as slip planes which can result in wafer warp, as well as cracks, bubbles, foreign particles or segregation zones and internal interfaces.

Abstract: A substrate includes an alignment key for forming features in or on both surfaces of the substrate which are in alignment with each other. The alignment key includes a plurality of adjacent but spaced apart small openings formed in one surface of the substrate through a P-type region at said one surface and a large opening extending through the substrate from its other surface to the P-type region. The larger opening exposes the smaller openings so that they can be seen from both sides of the substrate. The smaller openings are arranged to form an alignment mark.

Abstract: A process for forming a silicon-on-sapphire integrated circuit comprises forming a layer of a conformal dielectric material, such as silicon dioxide, over a sapphire substrate having at least one island of silicon on a major surface thereof; forming a layer of a planarizing material over the dielectric layer, anisotropically etching the planarizing material for a time sufficient to expose the surface of the dielectric layer overlying the island; etching the dielectric layer for a time sufficient to expose at least the top surface of the island; removing the remaining planarizing material, growing a thin layer of gate oxide on the exposed surface of the island and providing a patterned layer of conductive polycrystalline silicon thereover. The etching of the dielectric layer can be continued to at least partially expose the sidewall surface of the islands.

Abstract: A method of making a floating gate memory cell which relies on control gate to floating gate conduction to charge and discharge the floating gate. The gate oxide and inter-level dielectric thicknesses are independently controlled by using a mask which can compensate for the different substrate and floating gate oxidation rates.

Abstract: An additive that absorbs light at a given wavelength is added to a solder flux composition for use in laser soldering wherein the laser emits light of said given wavelength. The additive reduces the power required to melt the solder-flux combination and thereby improves soldering efficiency.

Abstract: Patterned glass layers which are defect-free and have smooth surfaces are formed by a method wherein a mixture of glass frit and a photoresist composition is applied to the surface of the substrate; the layer is photolithographically patterned by exposing and developing predetermined areas of the layer; then after development and prior to firing of the glass frit, the layer of material is subjected to treatment with a suitable plasma at a temperature below the thermal decomposition temperature of the photoresist composition to remove the photoresist composition from the portion of the resist layer remaining on the substrate; and then the remainder of the layer, consisting essentially of glass frit, is fired to form a smooth, defect-free, patterned glass layer over the surface of the substrate.

Abstract: A process is provided for forming a patterned layer of a polymeric material on a substrate for the lithographic processing thereof. A layer of polymeric material is formed on the substrate, embossed to form a pattern of peaks and valleys and dry etched to remove the residual polymeric material in the valleys, thereby exposing a portion of the substrate surface.

Abstract: A capacitor comprises a pair of electrodes with an insulator between the electrodes. The insulator has a primary dielectric with at least one void. A fill dielectric is in the void to improve yield.A method of making a capacitor comprises forming a first electrode, forming a primary dielectric having a void over the electrode, forming a fill dielectric in the void, and forming a second electrode over the dielectrics.

Abstract: A microwave planar switch matrix for selectively connecting various ones of M inputs to N outputs. The switch matrix includes a semi-insulative substrate on one side of which are conductors arranged in rows and columns, the interconnection of the rows and columns forming the intersections of the matrix, a plurality M.multidot.N of two-way active power dividers arranged in the rows near each intersection, respectively, and a plurality M.multidot.N of two-way power combiners arranged in the columns near the intersections, respectively, and M.multidot.N switches selectively connecting respectively one output of the power dividers to one input of the power combiners. Because the power dividers and power combiners utilize active components, net power gain through the matrix is possible. Air bridges separate the row and column conductors at the intersections.

Abstract: An input signal is applied to first and second logic gates to produce a first output out-of-phase with the input signal and a second output in-phase with the input signal. The first and second outputs are applied to a set/reset flip-flop whose output is applied to a transition detector to produce pulses having a minimum width when the input signal changes level for longer than some predetermined period Tl. The first and second logic gates are designed to have asymmetrical responses whereby input pulses of either polarity having less than the predetermined width Tl are treated as "noise spikes", are effectively filtered from the system, and do not cause a change in the state of the set/reset flip-flop.

Abstract: An array of electrically alterable floating gate devices arranged in rows and columns with each column of devices sharing a column conductor. Each row of devices is connected between two row conductors with adjacent rows sharing a common row conductor whereby in an array having N rows of devices there is a total of (N+1) row conductors. Input and output decoders connected to the row conductors enable the unique read-out of any selected element.

Abstract: A memory cell has a pair of cross-coupled inverters, such as a CMOS pair. Diodes are coupled in series with the transistors to reduce the possibility of radiation-induced currents in the transistors causing a change in state of the cell by providing resistance that increases the cell time constant. The transistors and the diodes are formed in the body of a semiconducting material. The diodes require at most only a small additional cell area as compared with a cell that does not have the diodes.

Abstract: A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. The layer of silicon is oxidized and the oxide layer is anisotropically etched until the top surface of the island is exposed, leaving oxide only on the sidewalls of the island. The exposed portion of the island is then oxidized to form a thin layer of gate oxide thereon. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

Abstract: A pyramid frequency analyzing technique is taught in which an input sampled temporal signal is convolved with a spatially localized, gradual rolloff kernel weighting function, which is subtracted from the input signal in each pyramid stage prior to the convolved signal having its sample density decimated and applied as an input to the next pyramid stage (rather than subsequent to the convolved signal having its sample density decimated as in a Burt Pyramid analyzer). In addition, a synthesizing technique is taught which provides additional high-frequency peaking in each stage thereof, not provided by a Burt Pyramid synthesizer.

Abstract: A semiconductor device includes a substrate of single crystalline silicon having the active regions of a semiconductor element, such as the source, drain, channel and gates, along one surface of the substrate, and a thin gettering region of a gettering material in the substrate. The gettering region is spaced from both surfaces of the substrate and is adjacent the active regions of the semiconductor element so as to getter contaminants in the substrate from the area of the substrate containing the semiconductor element.

Abstract: Charge integration is selectively interrupted in a semiconductor imager with thinned substrate, by modulating the electric field normal to its back-illuminated surface. This suppresses smear generated during field transfer in certain types of imager when exposed to high-energy images, for example. The thinned substrate is cemented with an electrically insulating epoxy to a glass backing plate bearing a transparent electrode, the potential on which is varied to modulate the drift field.