Patents Represented by Attorney, Agent or Law Firm Andrew J. Dillon
  • Patent number: 6058491
    Abstract: A method and system for handling detected faults in a processor to improve reliability of a computer system is disclosed. A fault-tolerant computer system is provided which includes a first processor, a second processor, and a comparator. Coupled to a system bus, a first processor is utilized to produce a first output. The second processor, also coupled to the system bus, is utilized to produce a second output. During the operation of the computer system, the second processor operates at the same clock speed as the first processor and lags behind the first processor. The comparator is utilized to compare the first and second output such that an operation will be retried if the first output is not the same as the second output.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: May 2, 2000
    Assignee: International Business Machines Corporation
    Inventors: Douglas Craig Bossen, Arun Chandra
  • Patent number: 6058426
    Abstract: The present invention is directed to a system and method for managing resources in an information handling system. The present invention provides a "one stop" local area network (LAN) based registration tool that provides a common set of user and administrative functions. The goal of the present invention is to give the end user the responsibility of managing her own resources. One aspect of the present invention is a method for managing resources in a distributed computing environment. Another aspect of the present invention is a client/server, object oriented, distributed computing product (DCE) based tool, with application agents being used to manage individual services. The present invention receives client requests for resources from an application. These resources may include a password to obtain access to the application or to resources controlled by the application. Rules are checked to determine if prior approval is needed to process the request.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: May 2, 2000
    Assignee: International Business Machines Corporation
    Inventors: Debbie A. Godwin, Kathryn I. Hansen
  • Patent number: 6058456
    Abstract: A method of allocating a cache used by a processor of a computer system between instructions and data is disclosed. Program instructions are loaded in the processor for monitoring relative usage of the cache by each value class and selecting a desired ratio of cache usage by the classes from among a plurality of available ratios, and cache blocks within the cache are evicted using a cache-replacement mechanism which restricts replacement of an evicted cache to a particular one of the classes of values (instruction or data) based on the desired ratio of cache usage. A multi-bit facility may be provided to indicate how to confine a selected victim to certain cache blocks, and the program instructions select the desired ratio of cache usage by setting the multi-bit facility. The cache-replacement mechanism can be a modified least recently used replacement mechanism. Different instruction/data ratios thereby may be provided, such as 1:1, 1:2, and 2:1.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: May 2, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Leo James Clark, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6055608
    Abstract: A method and system for speculatively sourcing data from a cache memory within a multiprocessor data-processing system is disclosed. In accordance with the method and system of the present invention, the data-processing system has multiple processing units, each of the processing units including at least one cache memory. In response to a request for data by a first processing unit within the data-processing system, an intervention response is issued from a second processing unit within the data-processing system that contains the requested data. The requested data is then sourced from a cache memory within the second processing unit by driving the requested data onto a system data bus before a combined response from all the processing units returns to the second processing unit.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: April 25, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6052778
    Abstract: A method and means for enhancing an embedded system includes means for and steps of executing a boot routine; activating a ROM loader routine; initializing an I/O subsystem; activating an embedded OS; creating a dynamically linked embedded system loader task, and having the embedded OS map the Global Coerced Memory (GCM) and the Global Shared Memory (GSM) into its address space so that it can access shared libraries; loading each of a plurality of executable programs, and mapping the GCM and the GSM into each executable program's address space so it is able to access shared libraries.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: April 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: Lee Emison Hagy, Grama Kasturi Harish, James Darrell Heath, Deepak Anantarao Kulkarni, William Francis Quinn
  • Patent number: 6052708
    Abstract: A multithreaded processor and a method for performance monitoring within a multithreaded processor are described. According to the present invention, execution circuitry within the multithreaded processor executes instructions in an active thread among first and second concurrent threads, while buffering circuitry buffers instructions and/or data of an inactive one of the first and second concurrent threads. Thread switch logic in the multithreaded processor switches threads by activating the inactive thread and inactivating the active thread. The operation of the multithreaded processor is monitored by a performance monitor, which records occurrences of an event generated by switching threads.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: April 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: William Thomas Flynn, Jack Chris Randolph, Troy Dale Larsen
  • Patent number: 6052108
    Abstract: A method of displaying text having improved useability is described which overcomes the difficulty of losing eye contact with an occurrence of a word in a line of text as the display is changed from one of disparate lines in one or more files to a new view of a single one of those disparate lines shown in context with the lines surrounding it in the file displayed above and below the selected occurrence. The display of the surrounding text in this way gives the illusion that the surrounding lines in the file were "filled-in" around the chosen line, such that the eye of the user does not have to move and re-locate the text of interest, since the text has not moved on the physical display screen.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: April 18, 2000
    Assignee: International Business Machines Corporation
    Inventor: Richard John Gadd
  • Patent number: 6052716
    Abstract: An apparatus and method are disclosed in a network navigator for rapidly returning to a search engine network page while searching through a hierarchy of networked pages displayed within a computer system interface. Initially, a list of commonly utilized search engine network addresses is compiled. Next, a hierarchy of network addresses accessed by the network navigator during a network navigating session is compiled. Thereafter, the hierarchy of network addresses is scanned until a network address among the hierarchy of network addresses is identified that corresponds to a search engine network address listed in the list of commonly utilized search engine network addresses. Finally, the network navigator jumps to the network address corresponding to the search engine network address.
    Type: Grant
    Filed: May 22, 1997
    Date of Patent: April 18, 2000
    Assignee: International Business Machines Corporation
    Inventor: Kevin Patrick Gibson
  • Patent number: 6049449
    Abstract: A computer includes a main enclosure for housing a plurality of computer components. A subenclosure or card cage for housing a planar circuit board, including a CPU means, and at least one accessory board may be removably secured within the main enclosure, wherein the subenclosure, planar circuit board, and accessory circuit board may be selectively removed from the main enclosure as a unit. A connection means is provided to releasably electrically connect at least the planar circuit board to one of the computer components housed within the main enclosure.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: William Vincent Cranston, III, Robert Allen Hood, Frederick Charles Yentz, Jose Platon Basco
  • Patent number: 6049334
    Abstract: A display window is displayed in association with at least one scroll bar at a terminal associated with a first user. Along the shaft of one ore more scroll bars, a distinctive visual location cue, such as a line in a color associated with a second user, is displayed to indicate the relative location within the shared data collection of the current and historical activity of a second user. A user may temporarily prohibit manipulation of a region within the shared data collection by other users by establishing a "lock" on the region. A lock region may comprise several lines of text, a portion of a graphical object, or other data within the shared data collection. To indicate the location of lock regions, lock region location cues are also displayed along the scroll bar.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: Cary Lee Bates, Jerry Allen Blades, Paul R. Day, Harvey Gene Kiel, Jeffrey Michael Ryan
  • Patent number: 6049329
    Abstract: A method of and system for facilitating stylus input into a text entry field in a pen-based computer system. The system detects a touch down of a stylus and determines whether the touch down is in a text entry field. Upon detection of movement of the stylus in the text entry field greater than a threshold, the system draws an include rectangle around the text entry field. The system sizes the include rectangle based on the size of the text entry field. The system interprets and completely inks any stroke of the stylus starting within the include rectangle within a predetermined timeout as an input to the text entry field. The system erases the include rectangle whenever it detects a stylus touch down outside the include rectangle, or the predetermined timeout expires without the system detecting a stylus touch down.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporartion
    Inventors: John Mark Zetts, Maurice Roger Desrosiers
  • Patent number: 6049849
    Abstract: A method and system for managing a cache including a plurality of entries are described. According to the method, first and second cache operation requests are received. In response to receipt of the second cache operation request, an entry among the plurality of entries is identified for replacement. In response to a conflict between the first and second cache operation requests arising because the first cache operation request specifies an entry among the plurality of entries including the entry identified for replacement, an entry among the plurality of entries other than the identified entry is replaced.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson
  • Patent number: 6049230
    Abstract: A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharge transistor, multiple input transistors, and a supplemental precharge transistor. Connected to a power supply, the precharge transistor receives a clock input. The discharge transistor is connected to ground and also receives the clock input. The input transistors, which are coupled between the precharge transistor and the discharge transistor, each receives a signal input. The supplemental precharge transistor is connected to the power supply and to a body of each of the input transistors. The supplemental precharge transistor also receives the same clock input as the precharge transistor.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Peter Gursen Klim, Binta Minesh Patel
  • Patent number: 6047186
    Abstract: The foregoing objects are achieved as is now described. Provided are a method and system for utilization with wireless communications systems having a cellular architecture covering a geographic area. The method and system accomplish their objects via the following. The geographic area is defined. One or more pairs of the sectors within the defined geographic area wherein a weak connection zone exists are determined. The geographic area is decomposed into two or more sub-areas wherein each sub-area is isolated from other sub-areas by the determined one or more pairs of sectors having a weak connection zone. A first of the sub-areas is selected. Frequency groups are assigned to each sector within the first selected sub-area such that signal to noise ratio is optimized. Thereafter, a second of the sub-areas is selected. One or more sectors within the second selected one of the sub-areas which are linked to sectors within the first selected sub-area are selected.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: April 4, 2000
    Assignee: Nortel Networks Corporation
    Inventors: Chang Yu, Xu Han, Seshagiri Rao Madhavapeddy, Sairam Subramanian
  • Patent number: 6046733
    Abstract: A computer-input stylus which provides thickness control when utilized in conjunction with a computer-implemented software-based drawing application. The input stylus includes a cylindrical body in a conical tip. A color display within the stylus is utilized to illuminate the conical tip with a color indicative of a currently selected color within the software-based drawing application, providing visual color feedback. Thickness selection is accomplished utilizing a thickness selection input actuator mounted to the cylindrical body of the input stylus. The thickness selection input actuator is utilized to vary the thickness of application of a selected color or pattern, while physically varying the thickness of the conical tip of the input stylus, in a manner analogous to utilizing a thicker tip brush.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: April 4, 2000
    Assignee: International Business Machines Corporation
    Inventors: David Carroll Challener, Palmer E. Newman
  • Patent number: 6045398
    Abstract: The battery accepting unit for a battery operated electric/electronic apparatus includes a plurality of positive terminals and a plurality of negative terminals. The battery accepting unit has a first position whereat a battery is connected by a pair of positive and negative terminals; a second position whereat a battery is connected by another pair of positive and negative terminals; a third position that can serve as both said first and said second positions; and a fourth position whereat a battery is connected by all positive and negative terminals. According to the battery accepting unit of the present invention, a battery pack can be exchanged without halting the power supply to an electric/electronic apparatus. Since an auxiliary power source, such as a sub-battery, is not required for an electric/electronic apparatus, a single power system, including a DC/DC converter and a charging circuit, can be provided.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: April 4, 2000
    Assignee: International Business Machines Corporation
    Inventors: Izuru Narita, Mitsuo Horiuchi, Hidefumi Suzuki, Mitsuru Ogawa
  • Patent number: 6046722
    Abstract: The method and system of the present invention may be utilized to enable a blind or visually impaired computer user to graphically select a displayed graphic element within a computer system display. A unique identifiable audible signal is associated with each displayed graphic element. A movable cursor element or pointer is displayed within the computer system display and a composite audible signal is periodically generated in response to the position of the movable cursor element. The composite audible signal preferably includes elements of each identifiable audible signal associated with each displayed graphic element within a predetermined radius of the location of the movable cursor element.
    Type: Grant
    Filed: December 5, 1991
    Date of Patent: April 4, 2000
    Assignee: International Business Machines Corporation
    Inventor: Frank Albert McKiel, Jr.
  • Patent number: 6043963
    Abstract: A low profile tape cartridge has a reel which rotates within an outer protective shell. The reel has flanges which define a slot containing a roll of magnetic tape. The shell only surrounds the reel along its circumference and the flat upper and lower surfaces of the flanges are exposed. When assembled, the reel and shell have axial thicknesses which are substantially equal. The shell moves between locked and unlocked positions for engaging and disengaging the reel. The cartridge uses and fits within a shell retainer for creating uniform spacing around the reel when the shell is in the unlocked position. The tape is accessed by loading a cartridge into the retainer in a tape drive. The tape drive unlocks the shell to rotate the reel and extract the tape. After use, the tape is retracted onto the reel and the cartridge is then returned to the locked position.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: March 28, 2000
    Assignee: International Business Machines Corporation
    Inventor: James Howard Eaton
  • Patent number: 6044209
    Abstract: A method and system for segmenting wires in the design stage of a integrated circuit to allow for the efficient insertion of an optimum quantity of buffers. The method begins by locating wires in the integrated circuit which interconnect transistors and then determining the characteristics of the transistor and the characteristics of the interconnecting wires. Next, the method computes a first upper limit for an optimum quantity of buffers utilizing total capacitive load wire and transistor characteristics, then the method computes a second upper limit for an optimum quantity of buffers assuming buffer insertion has decoupled the capacitive load. Finally, the method segments the wires by inserting nodes utilizing the greater of the first computation or the second computation. A determined upper limit on buffer quantity allows wires to be segmented such that the number of candidate buffer insertion topologies is manageable.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: March 28, 2000
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Stephen Thomas Quay, Anirudh Devgan
  • Patent number: 6041390
    Abstract: A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: March 21, 2000
    Assignee: International Business Machines Corporation
    Inventors: Peichun Peter Liu, Rajinder Paul Singh, Shih-Hsiung Steve Tung