Abstract: A compact wavelength monitoring and control assembly for a laser emission source is provided comprising a narrow bandpass, wavelength selective transmission filter element, of Fabry-Perot etalon structure, through which a non-collimated beam from the laser source is directed onto two closely spaced photodetectors. For wavelength stabilization, the differential output of the two photodetectors is used in a feedback loop to stabilize the wavelength of the laser source to a desired target wavelength. Through the angular dependence of the wavelength transmission of the Fabry-Perot etalon, a wavelength variation from the source is converted to a transmission loss, which is different for the two photodetectors, so that the wavelength change is detected as a differential power change. The device functions as an optical wavelength discriminator in which the detector converts optical energy to current for a feedback loop for controlling the light source.

Abstract: A voltage-controlled oscillator (VCO) includes a plurality of differential amplifiers which are ring-connected. Each amplifier includes two FETs, the sources of which are coupled. The coupled sources of each amplifier are connected to series-connected FETs which is part of a current mirror circuit. The series-connected FETs decrease transconductance of (i.e., increase impedance against) fluctuations in a power supply voltage, so that fluctuations in current flowing in the amplifiers are lessened. Thus, power-supply rejection ratio of the VCO increases and fluctuations in the VCO frequency are lessened.

Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO), a charge pump, a phase detector and a frequency detector. The phase detector detects the phase difference between an incoming signal and a VCO signal. The frequency difference between the incoming signal and a reference signal is detected by the frequency detector separately from the phase detector. During the process of attaining phase lock, the phase and frequency detectors operate simultaneously. The VCO signal is phase-locked to the incoming signal when it is present. When the incoming signal is absent, the VCO maintains a frequency close to an intended bit rate by frequency locking to a multiple of the reference signal. It, thus, avoids extreme system behavior and greatly assists rapid reliable phase lock when the incoming signal is applied following a period when it is absent.

Abstract: Binary and multiple-valued nonvolatile content addressable memories (NVCAMs) use ferroelectric capacitors as nonvolatile storage elements. The operation of the NVCAMs is accessed either in serial or in parallel. In a 2-bit NVCAM of a parallel access structure, search operation is performed by a simultaneous access a 4-level polarization of the ferroelectric capacitor. The total number of search operations is reduced.

Abstract: A charge pump circuit includes a current mirror circuit of current-sourcing and current-sinking FETs and a current steering circuit of cross coupled differential pairs of FETs. Nominal current flowing in the current-sourcing and current-sinking FETs is set. The current is for charging and discharging a capacitor of an external filter. During charging of the capacitor, the current through the current-sourcing FET is directed to the capacitor and the current through the current-sinking FET is directed from a low impedance voltage source. During discharging of the filter capacitor, the current through the current-sourcing FET is directed to the low impedance voltage source and the current through the current-sinking FET is directed from the capacitor. The current flowing in the current-sourcing and current-sinking FETs is nominally constant, regardless of the tri-state condition, charging or discharging, with the result that power supply noise is reduced.

Abstract: A Mach Zehnder (MZ) modulator with improved coupling of input and output fibers is provided. The MZ modulator combines the advantages of weakly guided input sections with strongly guided sections to optimize the coupling efficiency and selectivity of the device. Improved coupling between weakly and strongly guided sections of waveguide is provided by an intermediate tapered waveguide section which provides gradually changing mode confinement, which reduces the mode mismatch loss and therefore suppresses the reflection at the junction between the weakly and strongly guided sections of the waveguide.

Abstract: An improved ball grid array (BGA) package having EMI shielding is provided. In a BGA package a thermally conductive heat spreader provided by a conductive layer, and an electrical interconnection is provided between the electrically conductive heat spreader and solder balls of the array, for example by plated through holes extending through the dielectric body of the package. Thus in use of the package, when contacts are made from the array of solder balls to a corresponding array of contact areas of a substrate, a ground connection is simultaneously provided to the heat spreader through the solder balls. For example, one or more conductive contacts on the substrate may be connected to a ground plane of the substrate, and a corresponding solder balls of the package are interconnected to the heat spreader. Beneficially, the ground connection is provided by external rows of solder balls of the array extending around sides of package, or by clusters of solder balls surrounding balls for carrying signals.

Abstract: An monolithic integrated circuit comprising a transistor-inductor structure is provided having simultaneously noise matched and input impedance matched characteristics at a desired frequency. The transistor-inductor structure comprises a first transistor Q.sub.1 which may be a common emitter bipolar transistor or common source MOSFET transistor Q.sub.1, a second optional transistor Q.sub.2, a first inductor L.sub.E in the emitter (source) of Q.sub.1, and a second inductor L.sub.B in the base (gate) of Q1. The emitter length l.sub.E1, or correspondingly the gate width w.sub.g, of Q1 is designed such that the real part of its optimum noise impedance is equal to the characteristic impedance of the system, Z.sub.0, which is typically 50.OMEGA.. The first inductor L.sub.E, provides matching of the real part of the input impedance and the second inductor L.sub.B cancels out the noise reactance and input impedance reactance of the structure.

Abstract: An improved electrode structure compatible with ferroelectric capacitor dielectrics is provided. In particular, a multilayer electrode having improved adhesion to ferroelectric materials such as PZT is formed comprising a first layer of a noble metal, a second layer of another metal and a thicker layer of the noble metal, which are annealed to cause controlled interdiffusion of the layers forming a mixed metal surface layer having a rough interface with the dielectric layer. For example, the first two layers comprise relatively thin .about.200 .ANG. layers of Pt and Ti, and then a thicker layer of the main, first, electrode material is deposited on top. Non-uniform interdiffusion of the layers during annealing causes intermixing of the Pt and Ti layers at the interfaces forming a Pt/Ti alloy having a rough surface. The rough surface, and particularly hillocks formed at the interface, penetrate into the ferroelectric films, and anchor the electrode material to the dielectric.

Abstract: A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.

Abstract: An integrated circuit assembly and a method for distributed broadcasting of high speed chip input signals to a series of on-chip destination cells is provided, which eliminates the need for input buffers. A bufferless distributed broadcasting path is provided by matching the impedances off-chip conductive trace, i.e. a package trace, which together with interface circuitry forms a first transmission line, and on-chip conductive traces which form a second transmission line, to provide a constant impedance transmission line extending from a package trace to the far end of the on-chip trace. The method of bufferless distributed circuit (BDC) broadcasting is applicable to chip designs such as a crosspoint switch, parallel multiplier and distributed amplifier, and provides advantages of lower signal delay and power dissipation. In an experimental GaAs HBT 8.times.

Abstract: An integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

Abstract: A method of simulating AC timing characteristics at the pins of a device in of an application specific integrated circuit (ASIC) design is presented. The approach is fully automatic and is generalized, in the sense that both positive and negative Setup and Hold times and Propagation delays can be captured. The approach allows each bit of a data bus to be treated individually so as to be able to identify the worst case Setup time, Hold time and Propagation delay. Measurement is carried out in parallel for all data inputs and outputs. The need for manual intervention is eliminated and considerably reduces simulation time. Delay files are used through a call from a test bench, and the same testbench can be run on different delay information, namely pre-layout or post-layout delays.

Abstract: A gain-controlled amplifier for an integrated circuit includes a PNP gate controlled lateral bipolar transistor (GCLBT) which is configured in a common base configuration. The emitter electrode of the GCLBT is connected to a Bias-T having an inductor and a capacitor. The collector electrode of the GCLBT is coupled to a load capacitor, the capacitance of which is selected to alter the bandwidth of the amplifier. A gain control voltage is applied to the gate electrode of the GCLBT to control the amplifier gain. An input signal to be amplified is coupled to the emitter electrode of the GCLBT. An output signal, which is amplified in response to the gain control voltage, is provided from the collector electrode of the GCLBT. The gain-controlled amplifier can be used for an automatic gain control amplifier and also may be used for radio frequency and intermediate frequency amplifiers.

Abstract: An integrated circuit structure including dielectric barrier layer compatible with perovskite ferroelectric materials and comprising zirconium titanium oxide, ZrTiO.sub.4, and a method of formation of the dielectric barrier layer by sol gel process is described. The amorphous, mixed oxide barrier layer has excellent dielectric properties up to GHz frequencies, and crystallizes above 800.degree. C., facilitating device processing. In particular, the barrier layer is compatible with lead containing perovskites, including PZT and PLZT ferroelectric dielectrics for example for application in non-volatile memory cells, and high value capacitors for integrated circuits, using silicon or GaAs integrated circuit technologies.

Abstract: A gain-controlled amplifier has a transistor amplifier circuit and a transistor output circuit. The transistor amplifier circuit has an emitter coupled transistor pair for performing signal amplifying and another emitter coupled transistor pair which function as a current sink. The collectors of the transistors of both pairs are coupled to each other. The four transistors of the two pairs have substantially the same collector-emitter voltage vs. collector current characteristic. The output circuit is dc-coupled to the transistor amplifier circuit. An input signal to be amplified is fed to the base of a transistor which is connected to the coupled emitters of the amplifying pair of transistors. A current source is connected to the coupled emitters of the current sink pair transistors. The source current is substantially the same as the current flowing in the coupled emitters of the amplifying pair transistors.

Abstract: Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.

Abstract: An RC circuit with voltage controlled delay is provided. The circuit comprises a matched pair of RC delay elements, driven by outputs of a pair of amplifiers comprising a fixed gain amplifier and a variable gain amplifier having gain m so that the delay is dependent on a gain control voltage. Preferably, the circuit is operable in a regime wherein the gain m is linearly dependent on an input control voltage so that the circuit delay is also linearly dependent on the input control voltage. Advantageously, where the amplifier gain has non-linear dependence on a gain control voltage, a control voltage generator comprising a linear to logarithmic converter is used to provide an effective linear operation in response to an input control voltage. The circuit is preferably operated in differential mode, with RC circuit elements implemented simply as resistors and capacitors, and the amplifier and active elements provided by bipolar transistors.

Abstract: A charge pump circuit includes a current mirror circuit of current-sourcing and current-sinking FETs and a current steering circuit of cross coupled differential pairs of FETs. Nominal current flowing in the current-sourcing and current-sinking FETs is set. The current is for charging and discharging a capacitor of an external filter. During charging of the filter capacitor, the current through the current-sourcing FET is directed to the capacitor and the current through the current-sinking FET is directed from a low impedance voltage source. During discharging of the filter capacitor, the current through the current-sourcing FET is directed to the low impedance voltage source and the current through the current-sinking FET is directed from the capacitor. The current flowing in the current-sourcing and current-sinking FETs is nominally constant, regardless of the tri-state condition, charging or discharging, with the result that power supply noise is reduced.

Abstract: A transconductance amplifier for use in a low noise, microwave voltage controlled oscillator. The transconductance amplifier incorporates a linear amplifier having ratioed transistors to provide linearized gain. A tuning arrangement combines in-phase and out of phase currents in an inverse ratio to provide a constant D.C. current sum. The tuning circuit has been arranged to operate without a cascode stage such that the power supply voltage requirement is reduced from 5.0 volts to 3.3 volts.