Abstract: A method of selectively etching a layer of a refractory metal nitride, with application to formation of TiN local interconnects for VLSI integrated circuits, and particularly a method of selectively etching TiN relative to a refractory metal silicide. The method comprises the step of heating surfaces of the substrate to a selected etch temperature between 50.degree. C. and 200.degree. C. in a non-reactive gas and then exposing the heated substrate to reactive halogen species of a plasma having ion energies substantially less than 100 eV, and preferably below 30 eV. The etch selectivity is controlled by selecting a relatively low ion energy to reduce ion bombardment and heating effects during etching, and independently controlling the etch temperature in the heating step. The reactive species of the plasma are preferably generated by electron cyclotron resonance (ECR) excitation of a halocarbon containing gas, and heating comprises ion bombardment with a non-reactive gas.

Abstract: A method is provided for low pressure chemical deposition of tungsten and tungsten metallization for defining interconnects for an integrated circuit. A surface layer of tungsten is provided which has a low film stress and a smooth surface characterized by a low diffuse reflectivity and high specular reflectivity, to facilitate photo-lithography. Tungsten is deposited by reduction of WF.sub.6 with H.sub.2 and SiH.sub.4 in nitrogen. Control of the gas flow rates, pressure, temperature and H.sub.2 /WF.sub.6 ratio in the reactive gas mixture provides for tailoring of the structure and characteristics of a deposited tungsten layer to provide high step coverage or a smooth surface for forming an overlying layer of tungsten which may be patterned photo-lithographically for defining interconnect. In order to provide metallization providing both good step coverage in via and contact holes and smooth surface for deposition of surface metallization, a two-stage tungsten deposition is provided.

Abstract: A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension.

Abstract: A method is provided for forming a fully planarized trench isolated region in a semiconductor substrate for an integrated circuit, for example, a trench isolated field oxide region, or a trench isolated semiconductor region in which thin film semiconductor devices are formed. Planarization is accomplished by a chemical mechanical polishing process in which coplanar layers of a chemical mechanical polish resistant material are provided in a centre region of wide trenches as well as on the semiconductor substrate surface adjacent the trenches. The chemical mechanical polish resistant layer in the centre region of a wide trench forms an etch stop to prevent dishing of layers filling the trench during overall wafer planarization by chemical mechanical polishing. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuit structures.

Abstract: A method is provided for forming a conductive layer of ruthenium oxide layer RuO.sub.2. The RuO.sub.2 layer is formed from a coating of a precursor solution comprising a ruthenium (III) nitrosyl salt,subsequent heat treatment, and annealing at low temperature. The resulting layer of a tetragonal phase of crystalline ruthenium oxide is suitable for formation thereon of a perovskite structure ferroelectric material for applications in ferroelectric non-volatile memory cells. The chloride free process is compatible with processing for submicron device structures for bipolar, CMOS or bipolar CMOS integrated circuits.

Abstract: A method is provided for forming interconnect structures for ULSI integrated circuits. Preferably, a barrier layer of a conductive material which forms a seed layer for metal deposition is provided selectively on the sidewalls and bottom of interconnect trenches defined in a dielectric layer, and a conformal layer of metal is selectively deposited on the barrier layer within the interconnect trench. Advantageously, the metal layer forming interconnect comprises a layer of copper which is deposited by chemical vapour deposition from an organo-metallic precursor at low temperature. Etching back and planarization of the barrier layer and the metal layer is accomplished by chemical mechanical polishing.

Abstract: A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench.

Abstract: A method is provided for forming a capacitor structure for a memory element of an integrated circuit. The method comprises providing a first conductive electrode, forming a layer of a first dielectric material thereon, opening a via hole through the dielectric layer, providing within the via opening a capacitor dielectric having a higher dielectric strength than the first dielectric, the capacitor dielectric contacting the first electrode, planarizing the resulting structure and then forming a second conductive electrode thereon. Preferably, when the second dielectric comprises a ferroelectric dielectric material, sidewalls of the via opening are lined with a dielectric barrier layer to provide diffusion barrier between the ferroelectric and first dielectric layer. Advantageously, planarization is accomplished by chemical mechanical polishing to provide fully planar topography.

Abstract: A process is provided for forming a bipolar transistor and a structure thereof. In particular a single polysilicon self-aligned process for a bipolar transistor having a polysilicon emitter is provided. A sacrificial layer defining an opening is provided in a device well region of a substrate, and, after forming a self-aligned base region within the opening, emitter material is selectively provided in the opening to form an emitter-base junction. The sacrificial layer functions as a mask for ion implantations to form the base region, and if required, an underlying local collector region. The sacrificial layer is removed, to expose the well region adjacent sidewalls of the emitter structure. A self-aligned link region implant may be performed before forming isolation on exposed sidewalls of the emitter structure. Extrinsic base contacts are formed in the surface of the surrounding well region.

Abstract: A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench.

Abstract: A package is provided for an integrated circuit comprising a combined heat dissipating and electromagnetic shielding structure. Conveniently, the heat dissipation and shielding structure is a laminated composite structure including layers of several materials having complementary characteristics to provide high magnetic permeability, electrical conductivity, and thermal conductivity. For example, a sandwich structure of layers of copper/Kovar.TM./copper is effective in dissipating heat and reducing electromagnetic emission from ASICs for telecommunications applications, each dissipating in excess of 2 Watts. Preferably a substrate of the package includes a conductive die attach pad which may be grounded to bring a ground plane close to the integrated circuit. The composite electromagnetic shielding and heat dissipation structure is grounded to improve attenuation of radiated electromagnetic emission from the chip.

Abstract: A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension.

Abstract: A method and apparatus for wirebonding is provided. The apparatus is operable to perform a method of wirebonding leadwires between bond pads of a die of an integrated circuit (IC) and contacts of a leadframe of a IC package, in which the resulting bonded leadwires fan out towards corners of the package, and in which the sequence of formation of wirebonds is selected to minimize wirebonding tool-to-wire interference. In wirebonding a high lead count integrated circuit die to a leadframe of a package in which bonded leadwires fan out at angles approaching 45.degree. near corners of the package, for example as in a quad flat pack (QFP) format, bonding proceeds in sequence along each side to provide bonded leadwires to bond pads in a direction from a corner towards an intermediate position along one side and then from the opposite corner towards the intermediate position, in a direction of decreasing fan out angle.

Abstract: A method of tapering side walls of via holes and a tapered via hole structure for an integrated circuit is provided. Via holes having steep sidewalls are provided in an insulating layer overlying a conductive layer on a substrate, with an underlying conductive layer exposed at a bottom of each via hole. A protective layer is provided over the conductive layer in each via hole, and over the sidewalls. The via holes are then tapered by argon sputter etching to remove the protective layer and part of the insulating layer from the sidewall and around the peripheral edge of each via hole, thereby smoothly tapering the sidewall and providing a via hole increasing continuously in diameter from the bottom to the upper peripheral edge of the via hole.

Abstract: A weighted telephone base assembly and a method of providing a weighted telephone assembly. The telephone base assembly comprises a telephone housing having a base member, first and second printed circuit boards, and a weight having first and second parts. The base assembly is provided by locating and supporting the first part of the weight and the first circuit board upon the base member with the first circuit board overlying the first part of the weight in a space defined between the first and second parts of the weight; retaining the first circuit board upon the base member by latch means whereby the first part of the weight is removably retained upon the base member; and positioning the second circuit board on a support surface provided by a second part of the weight, so that the second circuit board is supported by the weight.