Abstract: Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.

Abstract: A method is provided for forming a crystalline perovskite phase of a ferroelectric dielectric material by a process of depositing a layer of amorphous ferroelectric precursor material and then annealing in an oxygen containing atmosphere in the presence of water vapor, preferably with the addition of a few percent of ozone and at a temperature of less than 500.degree. C. Advantageously, the method provides for formation of a ferroelectric material comprising lead zirconate titanate, with low film stress, high dielectric constant and low leakage current. The reduced thermal budget allows for increase flexibility in integration of ferroelectric materials, e.g. after a step of deposition of low melting point metal or metal alloy.

Abstract: A integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

Abstract: A gate controlled lateral bipolar junction transistor (GCLBJT) device for an integrated circuit and a method of fabrication thereof are provided. The GCLBJT resembles a merged field effect transistor and lateral bipolar transistor, i.e. a lateral bipolar transistor having base, emitter and collector terminals and a fourth terminal for controlling a gate electrode overlying an active base region. The device is operable as an electronically configurable lateral transistor. Advantageously a heavily doped buried layer provides a base electrode having a base contact which surrounds and encloses the collector. The surface region between emitter and collector is characterized by lightly doped regions adjacent and contiguous with the heavily doped emitter and collector, which effectively reduce the base width of the bipolar transistor and improve operation for analog applications.

Abstract: A polarization independent optical resonator comprising a phase-shifted grating structure is disclosed and analyzed. An application as a polarization independent optical wavelength filter with ultra-narrow bandwidth and fine tunability is described.

Abstract: A self-testable Digital Signal Processing (DSP) integrated circuit is described, using a Built-In Self Test (BIST) scheme suitable for high performance DSP datapaths. The BIST session is controlled via hardware without the need for a separate test pattern generation register or test program storage. Furthermore, the BIST scenario is appropriately set-up so as to also test the register file as well as the shift and truncation logic in the datapath. The use of DataPath-BIST enables a very high speed test (one test vector is applied per clock cycle) with no performance degradation and little area overhead for the hardware test control. Comparison between DP-BIST and scan-based BIST technique is also presented. DP-BIST is used a centralized test resource to test other macros on the chip and the integration of DP-BIST with internal scan and boundary scan is addressed.

Abstract: A lateral bipolar transistor comprising a self-aligned polysilicon base contact, and polysilicon emitter and collector contacts is provided. The self-aligned base contact significantly reduces the base width and therefore the base resistance compared with conventional lateral bipolar transistors, thus improving f.sub.t and f.sub.max. The polysilicon emitter and collector contacts improve the emitter efficiency and current gain, and allows for more flexible contact placement. The process is compatible with conventional double-poly bipolar processes.

Abstract: A buried layer contact for a integrated circuit structure is provided, with particular application for a contact for a buried collector of a bipolar transistor. The buried layer contact takes the form of a sinker comprising a fully recessed trench isolated structure having dielectric lined sidewalls and filled with conductive material, e.g. doped polysilicon which contacts the buried layer. The trench isolated contact is more compact than a conventional diffused sinker structure, and thus beneficially allows for reduced transistor area. Advantageously, a reduced area sinker reduces the parasitic capacitance and power dissipation. In a practical implementation, the structure provides for an annular collector contact structure to reduce collector resistance.

Abstract: An improved electrode structure compatible with ferroelectric capacitor dielectrics is provided. In particular, a multilayer electrode having improved adhesion to ferroelectric materials such as PZT is formed comprising a first layer of a noble metal, a second layer of another metal and a thicker layer of the noble metal, which are annealed to cause controlled interdiffusion of the layers forming a mixed metal surface layer having a rough interface with the dielectric layer. For example, the first two layers comprise relatively thin .about.200.ANG. layers of Pt and Ti, and then a thicker layer of the main, first, electrode material is deposited on top. Non- uniform interdiffusion of the layers during annealing causes intermixing of the Pt and Ti layers at the interfaces forming a Pt/Ti alloy having a rough surface. The rough surface, and particularly hillocks formed at the interface, penetrate into the ferroelectric films, and anchor the electrode material to the dielectric.

Abstract: A capacitor structure for an integrated circuit and a method of fabrication are described. The capacitor structure is defined by layers forming interconnect metallization and interlayer dielectrics. The latter are relatively thick, and provide high breakdown voltages. Multilevel metallization schemes allow for a stack of a plurality of electrodes to be provided. The electrodes may take the form of stacks of flat plates interconnected in parallel so that the capacitance is the sum of capacitances of alternate layers in the stack. Advantageously each electrode comprises a main portion and a surrounding portion having the form of a protecting ring, coplanar with the main portion of the electrode. The ring prevents thinning of the dielectric near edges of electrode during fabrication, to improve control of breakdown voltages for high voltage applications.

Abstract: A lateral bipolar transistor comprising a self-aligned polysilicon base contact, and polysilicon emitter and collector contacts is provided. The self-aligned base contact significantly reduces the base width and therefore the base resistance compared with conventional lateral bipolar transistors, thus improving f.sub.t and f.sub.max. The polysilicon emitter and collector contacts improve the emitter efficiency and current gain, and allows for more flexible contact placement. The process is compatible with conventional double-poly bipolar processes.

Abstract: A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a bottom electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used formation of the underlying integrated circuit.

Abstract: A package is provided for an integrated circuit comprising a dielectric body enclosing the integrated circuit chip having a plurality of conductive terminal members extend through the dielectric body. The dielectric body includes a magnetic shielding layer for shielding electromagnetic radiation from the integrated circuit. The magnetic shielding layer comprises a material having a high magnetic permeability and a high resistivity, so that the dielectric body absorbs electromagnetic radiation at frequencies generated by the integrated circuit and thereby attenuates electromagnetic emissions from the integrated circuit. Suitable materials having a high dielectric constant and high magnetic permeability include ferrites. Conveniently a shielding layer of ferrimagnetic material comprising a ferrite plate may be applied to surfaces of a conventional plastic or ceramic packaging material.

Abstract: A method of forming a semiconductor structure, and a structure thereof are provided. The method is based on a novel lift-off masking process, and has particular application for forming gate structures for FETs with sputtered metals. After providing a weakly bonded surface layer on the substrate, a multilayer masking layer stack is deposited, and patterned to define an opening with undercut sidewalls. The multilayer masking stack forms a heat resistant mask for nigh temperature deposition of one or more conductive layers, e.g. sputtered metals to form a gate metal stack for a FET. The undercut sidewalls of the mask create a discontinuity in the deposited metal layers. Preferential etching of the deposited metal layers occurs at the discontinuity, resulting in separation of the gate metal structure and the excess metal overlying the masking layers.

Abstract: A self-aligned single polysilicon bipolar transistor structure and a method of formation thereof are provided. The transistor has an emitter structure characterised by T shape defined by inwardly extending sidewall spacers formed by oxidation of amorphous or polycrystalline silicon, rather than the conventional oxide deposition and anisotropic etch back. Advantageously the method compatible with bipolar CMOS processing and provides a single polysilicon self-aligned bipolar transistor with a reduced number of processing steps. Further the formation of inwardly extending sidewalls defining the emitter width reduces the emitter base junction width significantly from the minimum dimension which is defined by photolithography, while a large area emitter contact is also provided.

Abstract: A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area. The method comprises selectively providing a tapered body of dielectric to mask a region of the substrate on which an emitter is to be formed. A conductive layer is provided around the tapered body to form base contact electrodes. The tapered body is selectively removed from the substrate without damaging the underlying silicon substrate, to leave a tapered opening; localized dielectric isolation is provided in the form of sidewall spacers on the first conductive layer. The tapered opening is filled with a layer of a second conductive material to form a second electrode i.e. an emitter structure.

Abstract: An integrated circuit is provided with particular application for high frequency modulation circuits, such as a mixer circuit, with reduced noise and gain. The circuit provides a novel application of a single device comprising a 4 or 5 terminal, gate controlled lateral bipolar junction transistor device, in the form of a merged MOS and lateral bipolar transistor. In a grounded base configuration, RF and LO signals are applied to the gate and emitter terminals respectively and provide for modulated output at the collector, and provides signal modulation with reduced noise compared with multi-device implementations of known mixer circuits using a summation circuit, diodes and FETs. Advantageously, operation of the device in the grounded base or grounded emitter configuration provides for strong modulation of the DC current gain, i.e. over 4 decades, as a function of gate voltage.

Abstract: A capacitor structure for a memory element of an integrated circuit is provided. The capacitor is formed within a via hole defined through a first dielectric layer, and comprises a bottom electrode defined by an underlying conductive layer, and a capacitor dielectric filling the via with a dielectric barrier layer lining the via and separating the capacitor dielectric from the first dielectric layer. The capacitor dielectric is characterized by a material with high dielectric strength, preferably a ferroelectric material. An overlying conductive layer defines a top electrode contacting the capacitor dielectric. The barrier layer may comprise dielectric sidewall spacer formed within the via, or alternatively may comprise a region of mixed composition formed by interdiffusion of the first dielectric layer and the capacitor dielectric. The resulting capacitor structure is simple and compact, and may be fabricated with known CMOS, Bipolar or Bipolar-CMOS processes for submicron VLSI and ULSI integrated circuit.

Abstract: A process is provided for forming a bipolar transistor and a structure thereof. In particular a single polysilicon self-aligned process for a bipolar transistor having a polysilicon emitter is provided. A sacrificial layer defining an opening is provided in a device well region of a substrate, and, after forming a self-aligned base region within the opening, emitter material is selectively provided in the opening to form an emitter-base junction. The sacrificial layer functions as a mask for ion implantations to form the base region, and if required, an underlying local collector region. The sacrificial layer is removed, to expose the well region adjacent sidewalls of the emitter structure. A self-aligned link region implant may be performed before forming isolation on exposed sidewalls of the emitter structure. Extrinsic base contacts are formed in the surface of the surrounding well region.

Abstract: A lateral bipolar transistor is provided in which the active base region comprises a layer of a material providing a predetermined valence band offset relative to the emitter and collector regions, to enhance transport of carriers from the emitter to the collector in a lateral manner. In particular, a silicon hetero-junction lateral bipolar transistor (HLBT) is provided. The lateral bipolar transistor structure and method of fabrication of the transistor is compatible with a bipolar-CMOS integrated circuit. Preferably the base region comprises a silicon-germanium alloy or a silicon-germanium superlattice structure comprising a series of alternating layers of silicon and silicon-germanium alloy.