Abstract: For reducing the complexity of adaptive systems such as equalizers, echo cancellers and clock recovery systems, errors are often determined only once per n samples, where n is an integer. If the input signal of such an adaptive system comprises cyclostationary components, it may occur that the adaptive system does not converge to a desired value. By selecting n in such a way that the greatest common divisor of n and the cyclostationary period m of the input signal is equal to 1, convergence of the adaptive system is ensured.

Abstract: Conventional microprocessors await the data on the bus for acceptance for a given number of processor clock signals after accessing an external device, notably after a read instruction for an external data memory. When a comparatively slow memory is used in conjunction with a fast microprocessor, it may occur that the data is not yet present at the anticipated instant. In microprocessors in which no hold state is provided it is known to reduce the clock frequency during the reading of the external memory until the data is actually available. However, this results in a fluctuating mean clock frequency of the microprocessor so that internal timing members, controlled by the clock, cannot determine defined periods of time. In accordance with the invention, the clock frequency is reduced during the part of the operating cycle of the microprocessor during which an external device can be accessed, the microprocessor operating at the maximum clock frequency during the remainder of the cycle.

Abstract: In detecting patterns in data arranged in a spatial field of one, two or higher dimension, a pattern contrast signal is evaluated which measures the similarity to the pattern of the data around a location in the spatial field. The pattern is subsequently detected if the pattern contrast signal is sufficiently strong. There is, however, a risk of erroneous detection when a coincidental noise configuration causes an increased pattern contrast signal. The invention provides for a method and apparatus to discriminate against such erroneous detections. For this purpose, the method observes the extent to which a would-be pattern dominates the effect on the pattern contrast signal of the distribution of data values in the surroundings of the location, this distribution being taken to be typical of noise. In one embodiment, this is done by confirming that the pattern is sufficiently strong to suppress any other would-be pattern detections in the surroundings.

Abstract: Communication of digital information between digital systems (2, 3) comprising clock generators (8, 9) is effected via storage in memory locations a1 to a8 and b1 to b8 of a cyclic buffer 4, in which, in succession, the information is written and read on a time base determined by the various clock generators (8, 9). Pointers stored in pointers (12, 13) determine the memory locations to be read out or written. If the pointers have become equal as a result of phase deviations of the clock generators (8, 9), this is detected by an address distance monitoring means (14) and made unequal and set to a maximum difference value relative to each other. The difference value amounts to half the number of memory locations n in a row of the buffer 4. For full duplex transmission the buffer 4 preferably comprises a double row of memory locations a1-an and b1-bn respectively.

Abstract: A method to compress, store, and retrieve bibliometric information on multiple sources of text is presented. The compression consists of 2 parts, and may use any one of the many ordering-based bibliometric laws for sources of text. The first compression part comprises of the storage of bibliometric information on the items from a text source, using the rank of the items in the ordering relation as defined in the bibliometric law as an indication of the bibliometric information. The second compression part efficiently uses pointers and tables to get rid of redundant information. As an application, a posting compression method is presented for use in term weighting retrieval systems. The first compression uses a postulated rank-occurrence frequency relation for the document in question that has as only variable the document's length, for example Zipf's law that states that the product of rank and frequency is approximately constant.

Abstract: In the future, integrated wideband networks, especially the arrangement of switching networks and switching network controls, will be of particular importance. To avoid bottle-necks in the switching network a number of different measures or combinations thereof are taken. These measures include that: a) the transfer rate of the switching network is enlarged by a structural change; b) the switching network is multiplied; c) the input buffers are re-arranged; and d) the allocation strategy is changed.

Abstract: This system is formed, on the one hand, by a transmitting section (1) comprising coders (CA, CB, CC) for coding according to an error detection code the data to be transmitted over the main channels and comprising a coder (CS) for an auxiliary channel (CHS) and, on the other hand, a receiving section (2) constituted by error detecting circuits (DA, DB, DC, DS). In the transmitting section there is provided a combining circuit (20) for combining the data to be transmitted over the main channels, whereas the auxiliary channel is used for transmitting the combined data. In the receiving section there are provided decombining circuits (USA, USB, USC) for producing replicas of the transmitted data for each of the main transmission channels on the basis of data transmitted over the auxiliary channel. These replicas are used in case of failing transmission channels.

Abstract: The described circuit arrangement for removing stuff bits from a frame-structured signal which is available in n parallel bits, comprises a memory circuit (2) which is supplied with the parallel bits (1b). The memory circuit (2) is followed by a controllable selection circuit (3) having n outputs (3a). A control circuit (9) produces control signals (9b, 9c), which determine which bits stored in the memory circuit are transported to the n outputs (3a) of the selection circuit (3). The memory circuit (2) comprises only n delay elements by which each of the n parallel bits (1b) is delayed for the duration of one bit. So as to provide that n delay elements will be sufficient, the control circuit (9) is to block at predetermined time intervals the acceptance of new bits in one or a plurality of delay elements.

Abstract: A digital echo canceller has a receive path (2) and a send path (3) and comprises combining apparatus (10) for forming a send output signal [r(k)] as the difference between the signal [z(k)] applied to the send input (SI) and a replica signal [e(t)] used for cancelling an additive echo signal [e(k)] at the send input (SI) that has developed in response to a receive input signal [x(k)] applied to the receive input (RI), which echo canceller at least includes transforming apparatus (13, 15) for transforming the receive input signal [x(k)] and the send output signal [r(k)]; transforming apparatus (14) for transforming the replica signal [e(k)]; a digital adaptive filter (9) which has a number of filter coefficients for generating the replica signal [e(t)] in response to the receive input signal [x(k)] and the send output signal [r(k)], adaptation apparatus (12) for determining for each block m, adaptation components [A(p;m)] for each of the filter coefficients [W(p;m)] in response to the receive input signal [x(

Abstract: A demultiplexer for an isochronous multiplex signal is described which signal consists of isochronous sub-signals interleaved block by block. The demultiplexer comprises a read-write memory (MXA, MXB, MXC, MXD) as well as a read-write control (ST). The proposed circuit arrangement may be devised in a highly advantageous manner as an integrated circuit because it is has been considered that, for example, the manufacturers of gate arrays leave the user only the choice of using building blocks depicted in a catalogue. These building blocks constitute the function blocks (MXA to MXD) which are provided for partitioning an STM-16 signal into four sub-signals (STM4A, STM4B, STM4C, STM4D). The control signals for these function blocks (TL15:0, Z(3:0), T311, T622) are produced by a control circuit (ST) whose central module is a four-stage cyclic counter. The necessary control signals are derived from the count of the cyclic counter by means of addressable demultiplexers.

Abstract: A silicon lithium x-ray detector has a new shape. The shape includes a front and a back. At the back, a center portion of thickness H is surrounded by a groove of depth D and an outer rim having a height h less than H.

Abstract: A bidirectional coherent optical transmission system comprises two stations (I and II) each having only a single laser (2, 9), part of the light signal generated by the laser being fed to a glass fibre T and another part of the light signal generated by the laser being used for mixing the received light signal down to an intermediate frequency by means of a photoelectric diode (4, 11). In contradistinction to the prior art transmission system, in the system according to the invention the light signal is modulated by applying a modulation signal to each of the lasers (2, 9).

Abstract: A data processing device for selecting data words which are contained in a dictionary and which are nearest to a data word to be processed according to a correspondence criterion. The device includes: first apparatus for segmenting the space enclosing the assembly of data words of the dictionary; second apparatus for generating, for each segment, sub-dictionaries by making an arbitrary segment correspond, in accordance with the correspondence criterion, to words of a sub-dictionary; third apparatus for utilising the sub-dictionaries by determining, for an arbitrary data word to be processed, the segment with which it is associated, followed by determination, in accordance with the correspondence criterion, of that word or words among the words of the sub-dictionary associated with the segment which corresponds (correspond) best to the arbitrary data word to be processed. Segmentation can be realised by means of a layered or tree-like neural network.

Abstract: A circuit arrangement for adapting the bit rates of two signals to each other and which comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7,8). In order to largely avoid jitter in the signal that has been read, a balancing counter (14) is provided which, on average, is stopped as often as the write address counter (7) is, but runs more smoothly than the write address counter. The means for controlling the operation of the balancing counter (14) comprise comparator circuits (12E, 12F, 12G) by means of which the operation of the frame counter (12) is monitored, an up/down counter (19) as well as various gates (11, 13, 17, 18).

Abstract: A multi-station communication bus system allows for the use of several master stations by way of an arbitration organization. A message contains a master address which is subjected to an arbitration operation, a slave address with space for a slave address acknowledge bit, a control signal with space for a control acknowledge bit, and one or more data bytes. Per data byte an indication of the "last" byte is also transmitted and space is reserved for a data acknowledge bit. When a data acknowledge bit is not correctly received, the data byte in question is repeated until at the most the maximum frame length is reached. The remainder of a message is then placed in a next frame. If an address or control acknowledge bit is not correctly received, the relevant frame is terminated. In case of a plurality of bytes in a message, the first frame thereof has a lock control signal that is activated upon communication of at least one data byte.

Abstract: An arrangement of data cells which stores at least one matrix of data words which are arranged in rows and columns, the matrix being distributed in the arrangement in order to deliver/receive, via a single bus, permuted data words which correspond either to a row or to a column of the matrix. Each data cell is connected to the single bus via series-connected switches which are associated with a respective addressing mode, the switches which address a same word of a same mode being directly controlled by a same selection signal. Circulation members enable the original order of the data on the bus to be restored. An arrangement of this kind is used in a layered neural network system for executing the error backpropagation algorithm.

Abstract: A communication system comprises a central processing unit (1) and a plurality of N communication stations (2.1, 2.2, . . . , 2N), in which the central processing unit and the communication stations are coupled over an uplink signal line (3) and a downlink signal line (4). The downlink signal (FIG. 3) on the downlink signal line has the form of successive frames, each frame comprising M signal blocks (SB.sub.m), the first signal block in a frame comprising a synchronizing word (sync word) (22), the signal blocks all having space for storing audio information in the form of p audio words (21), the M-1 signal blocks not comprising a sync word further having space for storing control information, the control information in a signal block belonging to a communication station containing downlink assign information (a.dl+m) denoting which audio words in the signal blocks in a frame are destined for said communication station. The uplink signal (FIG.

Abstract: An x-ray detector assembly is improved by covering the detector holder with a dielectric film to prevent contamination of the sides of the detector without covering the front of the detector. The film does not hermetically seal the detector holder.

Abstract: A programmable processing device has a built-in a program memory (14) for storage of data including program instructions for controlling a functional unit (20) of the device. The device also includes signature generating means (18) for combining data read from all locations of the memory (14) during a memory test sequence, to generate a signature word which can be used to verify correct programming and operation of the memory. The device includes means for supplying the generated signature word to an instruction decoding means (20) at the end of the memory test sequence for execution as a normal program instruction. The signature word thus directly determines subsequent operation of the device, enabling the verification result to be communicated externally without the need for a dedicated data path for communicating the signature value itself outside the device. Any desired signature word/instruction can be achieved by including a seed word in the stored data.

Abstract: According to the invention, the chip card issues a first certificate comprising its letter of credentials (Crc), an exponential (X), an optional message (M), these quantities being signed. The security module verifies the signature and in return issues a second certificate containing its letter of credentials (Crm), an exponential (Y), an optional message (M'), a cryptogram (C), these quantities being signed. A common secret key is constituted between the card and the security module by the exponentials and allows the card to interpret the cryptogram addressed to it and to act in accordance therewith.