Abstract: The arrangement multiplexes channels of differing bit rates onto a multiplex line. Channels are split according to a table assembled in a channel splitter. The table has a plurality of lines numbered by an index j. Each line j contains j .DELTA..sub.i, j .DELTA.S, and j .DELTA.X, where .DELTA..sub.i =di/dMAX, .DELTA.S=dS/dMAX, and .DELTA.X=dX/dMAX, i is an index numbering the multiplex channel, di is the bit rate of the channel i, dS is the rate of the service data, dMAX is the fastest of the di and dS, ##EQU1## and dTDM is the bit rate of the multiplex line. The table is assembled until each quantity on the line j exceeds VS, where VS=1+.epsilon.. Access to the multiplex line is given to the channel for the values of i where j.multidot..DELTA..sub.i >kVS+.epsilon., where k is an integer which is incremented each time access is given to the multiplex line and .epsilon. is a fixed value preferably equal to zero.

Abstract: Improved materials for the electrodes of arc discharge devices reduce arcing damage.The materials have a ductile-to-brittle transition temperature at or below the normal operating temperature of the devices.

Abstract: A communication system such as a digital cordless telephone system comprises primary (or base) stations (PS) and secondary stations (SS). The primary stations over a local area are coupled to a system controller (14 or 15) which interfaces with the PSTN. A TDMA method is used for forward and reverse transmissions between a primary and a secondary station. For digitized speech transmission normally one duplex voice channel formed by one forward time slot (or physical channel) and one reverse time slot (or physical channel) in each frame is allocated for the transaction. For fast data rates it is desirable that additional duplex voice channels be made available quickly for the transmission of a fast data message, after which the additional duplex voice channels can be relinquished. In order to facilitate the rapid set-up of a data transaction, a map store in each data secondary station lists the usage and quality of all the duplex voice channels.

Abstract: Digital data processing apparatus for use as a three-layer perceptron comprises three sets of processing cells (29A-29D, 29E-29H, 29I-29L). The data inputs of the cells of each set are connected to a respective common data bus (30,32,33) and the data outputs of the cells of each set are connected to a respective common data bus (32,33,34). Input data applied sequentially to the input bus (30) are processed in parallel by the cells (29A-29D) of the first set under the control of a clock pulse generator arrangement (35) which controls synchronized read-out of respective weighting factors from a store included in each cell, accumulation of the thus weighted items of input data, latching of the processing result in each cell, and subsequent read-out of the latched results onto the relevant output bus (32). The read-out results constitute input data for the cells (29E-29H) of the next set, which operate in the same way, as do the cells (29I-29L) of the final set.

Abstract: A circuit arrangement for establishing conference connections comprising conference units is described, which units are linked to form a loop (L). In this loop (L) sum codewords consisting of sample values of the signals of all participants in a conference are transmitted from one conference unit to the next. In each conference unit a sum codeword is updated so that the sample value of a conference signal from the previous loop travel is replaced by the current sample value. In order to enable the monotoring of a travel of sum codewords through the loop with a circuit arrangement of this type and in order to have the sum codewords pass through the loop in a predetermined brief period of time without a necessity for a synchronization of individual processing modules of the conference units, the function of one or more conference units is taken over by a programmed processor (P1 to P4). The exchange of data between the conferees and the processors is controlled by means of an interface circuit (PO).

Abstract: A work station controller module for use in an industrial manufacturing system is described. The manufacturing system is hierarchically organized. A superior level is covered by a host machine, a lower level by automation modules that fulfill the manufacturing and transport primitives. The controller module receives higher level commands for decomposition into lower level commands. It also receives lower level status signals for aggregation into higher level status signals. It also exchanges product exchange requests and product exchange acknowledgements with a product transfer system. It further receives operation names and process data from a product development system and status aggregation rules and command decomposition rules from a product preparation system. These rules govern the decomposition/aggregation cited earlier.

Abstract: A circuit arrangement for converting the bit rate of a frame structured input signal to a predetermined nominal bit rate. The data bits of the input signal are written into an elastic store (6) at the bit rate of such signal by means of a write address counter (7), and subsequently read out again therefrom by means of a read address counter (8) at a rate within a tolerance range of the nominal bit rate. A phase comparator (16) determines the distance between the counts of such counters and produces a control error signal corresponding to such distance. In order to minimize jitter of the read out signal, the control error signal is supplied to a control circuit (18) which controls the clock produced by a clock generator (17) for the read address counter (8). The clock generator circuit includes a frequency controllable oscillator, the output of which serves as the read clock.

Abstract: In a detecting patterns in data arranged in a spatial field of one, two or higher dimension, a pattern contrast signal is evaluated which measures the similarity to the pattern of the data around a location in the spatial field. The pattern is subsequently detected if the pattern contrast signal is sufficiently strong. There is, however, a risk of erroneous detection when a coincidental noise configuration causes an increased pattern contrast signal. The invention provides for a method and apparatus to discriminate against such erroneous detections. For this purpose, the method observes the extent to which a would-be pattern dominates the effect on the pattern contrast signal of the distribution of data values in the surroundings of the location, this distribution being taken to be typical of noise. In one embodiment, this is done by confirming that the pattern is sufficiently strong to suppress any other would-be pattern detections in the surroundings.

Abstract: A logic analyzer is provided with probes (20) deriving the signals to be tested which are introduced into a digitizer (22) provided with comparators which carry out a digitization according to a logic system having two states. It comprises a change-over circuit (21) arranged between the probe and the digitizer, which permits associating several or all comparators with a given signal to be tested to extend its digitization to a multi-level logic system. The change-over circuit (21) is constituted by a matrix of MOS transfer gates or field effect transistors (FET's). When the multi-level logic system has at least one medium state limited by two references, the medium state is displayed on a display device (24) according to a straight line or a monotonic curve joining the two references between the beginning and the end of the medium state. When the duration of the medium state exceeds a predetermined duration, the display device (24) is switched on to display the medium state.

Abstract: The described demultiplexer is intended for a serial and isochronous multiplex signal consisting of Q isochronous tributary signals interleaved bock-by-block, each block containing K bits. An associated multiplexer is also described. In order to keep the required memory capacity in a demultiplexer as small as possible, a write/read memory (5) is utilized, into which the bits of the multiplex signal are cyclically written and from which, simultaneously, the bits of the tributary signals are read out cyclically. A write/read control (4) coordinates the writing and reading processes in a manner such that no collisions occur. In an exemplary embodiment the bits of the multiplex signal are written into the write/read memory (5) bit-by-bit by means of a serial-to-parallel converter (2). Reading is effected bit-by-bit while utilizing read logics (81, 82, 83, 84) which are also controlled by the write/read control (4) via addresses.

Abstract: A multiple user radio system comprising at least one primary station and a plurality of secondary stations by way of a control channel. The primary station in use sets a value, in a transmitted message from which a secondary station wanting to economise on power can derive a period during which it can switch-off at least its radio section. The radio system may comprise a radiopaging system or a radio trunking system using an Aloha protocol. In the case of a radio trunking system using an Aloha protocol, the value comprises the Aloha number.

Abstract: A method of planning optimum routes on the basis of successively selected sub-sets of the total topographical and traffic information, so-called buckets, which method anticipates which buckets will be of importance in the near future for the calculation of the navigation data, and navigation system comprising a route planner for carrying out such a method.

Abstract: An arrangement of data cells which stores at least one matrix of data words which are arranged in rows and columns, the matrix being distributed in the arrangement in order to deliver/receive, via a single bus, permuted data words which correspond either to a row or to a column of the matrix. Each data cell is connected to the single bus via series-connected switches which are associated with a respective addressing mode, the switches which address a same word of a same mode being directly controlled by a same selection signal. Circulation members enable the original order of the data on the bus to be restored. An arrangement of this kind is used in a layered neural network system for executing the error backpropagation algorithm.

Abstract: A method and system for authentication of accreditations and of messages with zero-knowledge proof and for the signing of messages, and a station for use in such system, in particular executed as a smart card station.Instead of using multiple accreditations and an iterative process of verification, use is made of a comprehensve accreditation (high exponent p) and a number D is drawn at random, which number is within the range between 0 and p-1. The operations of verifiction proceed by the computation of the D-th power of the inverse accreditation B.Application in particular, to smart cards and, more specifically, to bank cards.

Abstract: For obtaining an output signal which is independent of the polarization direction of the received signal in a receiver for polarized electromagnetic signals, the received signal is split up into two components having a mutually orthogonal polarization direction before these signals are converted to an intermediate frequency. For combining, subsequent to demodulation, the two intermediate-frequency signals to a baseband signal which is independent of the polarization direction, a demodulator is used having a quadratic relation between input and output signals. For obtaining this quadratic relation, the intermediate-frequency signal is split up by an amplifier 20 into two signals having a mutually identical amplitude and mutually opposite signs. Consequently, the odd order terms in the sum of the currents through the diodes 27 and 28 will have opposite signs relative to the odd order terms in the sum of the currents through the diodes 36 and 37.

Abstract: A method of controlling a plurality of peripheral units from a single control unit, a program being stored in a memory of the control unit and the peripheral units being in a position to communicate with one another and with the control unit over a common bus in successive frames of a time-division multiplex system, each frame in the time-division multiplex system being subdivided into a number of time slots at least equal to the number of peripheral units, the same time slot in each frame being assigned to a peripheral unit, specifically each peripheral unit transferring information about its status, which information is initiated by the peripheral unit itself, to the memory in the control unit during or at least immediately prior to the time slot assigned to the peripheral unit in the next frame.

Abstract: Process for the management of address words which determines destination addresses for the switching of data on the basis of input address words of (M+N) bits. The process includes the following steps:on the basis of two input address words, separation of each one of these words into two fields of M and N bits respectivelycombination of these fields in accordance with a law of composition of non-commutative groups in order to deliver destination addresses emanating from the combination.The composition laws which are implemented necessitate only simple operations. Also a unit for the management of address words. This permits reduction of the addressing periods in searching for data, for example when they are stored in memory.

Abstract: A computer method and apparatus for combining a brush object element with a trajectory object element in a graphics display system. The brush has a reference point that moves along a trajectory, and any point in application coordinates that is at any position covered by the brush, is assigned an -inside- indication. The trajectory may be non-closed or closed, in which latter case it may also govern an -inside- indication. The approach is point driven, which leads itself to acceleration by means of array calculations.

Abstract: In the framework of the development of future, integrated wideband networks, specifically the arrangement of the switching networks and switching network controls is of particular importance.In a switching network arranged in accordance with a space-division multiplex switching network each switching point comprises a comparator, comparing the addresses of the trunk lines arranged column-by-column to the routing information. When there is multiple correspondence in a column a decision circuit assigned to the trunk line decides the order in which the switching points are to switch. In addition, an input buffer is connected to each supply line, in which buffer the blocks are temporatily stored until they can reach one of the trunk lines. To avoid the occurrence of bottle-necks in the performance of the switching network an input buffer is assigned to each switching point or the switching network is arranged column-by-column and built up of units of equal structure.

Abstract: A multi-station communication bus system allows for the use of several master stations by way of an arbitration organization. A message contains a master address which is subjected to an arbitration operation, a slave address with space for a slave address acknowledge bit, a control signal with space for a control acknowledge bit, and one or more data bytes. For each data byte an indication of the "last" byte is also transmitted and space is reserved for a data acknowledge bit. When a data acknowledge bit is not correctly received, the data byte in question is repeated until at the most the maximum frame length is reached. The remainder of a message is then placed in a next frame. If an address or control acknowledge bit is not correctly received, the relevant frame is terminated. In case of a plurality of bytes in a message, the first frame thereof has a lock control signal that is activated upon communication of at least one data byte.