Patents Represented by Attorney Anthony J. Sarli, Jr.

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  • Selective titanium silicide formation
    Patent number: 4619038
    Abstract: A process for selective formation of a titanium silicide, TiSi.sub.2, layer at high temperatures and low pressures via chemical vapor deposition during semiconductor device manufacturing. At 700.degree. to 1000.degree. C. and 0.5 to 1.5 torr, TiSi.sub.2 deposits only on exposed silicon or polysilicon surfaces and not at all on neighboring silicon dioxide. The process provides an excellent means of providing low resistivity interconnects without a mask step or subsequent annealing and removal of unreacted titanium.
    Type: Grant
    Filed: August 15, 1985
    Date of Patent: October 28, 1986
    Assignee: Motorola, Inc.
    Inventor: Faivel S. Pintchovski
  • Row decoder
    Patent number: 4620299
    Abstract: A logic decoder provides a true output signal at a first logic state when selected during an active cycle and during an inactive cycle, and at a second logic state when deselected. The logic decoder also provides a complementary output signal. A word line driver circuit couples decoded address signals to respective word lines when the output signal is in the first logic state. A coupling circuit couples one of first and second word lines to ground during the active cycle. A coupling transistor couples the first and second word lines together in response to receiving the complementary output signal at the first logic state.
    Type: Grant
    Filed: March 4, 1985
    Date of Patent: October 28, 1986
    Assignee: Motorola, Inc.
    Inventors: Scott Remington, William L. Martino, Jr.
  • Dual page memory system having storage elements which are selectively swapped between the pages
    Patent number: 4618946
    Abstract: In a dual page memory system sharable by first and second processors, a plurality of storage elements are assigned to first and second pages accessible by the respective processor. An address decoder decodes addresses provided by either of the processors, and provides a selection signal corresponding to a predetermined storage element in each of the pages. A page selector couples the selection signal to the storage element in the page assigned to that processor. An access controller provides access to that processor to the storage element to which the selection is coupled. An assignment controller is provided to selectively swap corresponding storage elements between the pages.
    Type: Grant
    Filed: September 17, 1984
    Date of Patent: October 21, 1986
    Assignee: Motorola, Inc.
    Inventors: Wendell Little, Tim Williams
  • Monotonic A/D converter which minimizes circuitry for high order bit conversion
    Patent number: 4618852
    Abstract: An N bit converter, where N is an integer, is provided for effecting A/D and D/A conversions by utilizing a capacitor array and a resistor voltage divider string. The converter may be linear or nonlinear and the structure remains monotonic independent of the accuracy of the converter. Although monotonic, device count is minimized and only 2.sup.(N/2) stages are required to implement an N bit linear converter. Reduction of the number of circuit elements is achieved, in part, by shared use of decode circuitry for the most significant and least significant bits of the N bits.
    Type: Grant
    Filed: February 27, 1985
    Date of Patent: October 21, 1986
    Assignee: Motorola, Inc.
    Inventors: Stephen H. Kelley, Mathew A. Rybicki
  • Output compare system and method automatically controlilng multiple outputs in a data processor
    Patent number: 4618968
    Abstract: An output compare system and method for automatically controlling multiple outputs in a data processor includes an output compare mask register for holding a set bit therein. An output compare data register is coupled to a control output of the output compare mask register for holding a data bit therein. Apparatus for initiating an output compare function are coupled to a control input to the output compare mask register whereby the data bit will be transferred to an output of the data processor if the set bit is present. The system and method allow for simultaneous utilization of multiple output compare functions to achieve one-cycle-wide pulses on a timer output pin.
    Type: Grant
    Filed: November 4, 1983
    Date of Patent: October 21, 1986
    Assignee: Motorola, Inc.
    Inventor: James M. Sibigtroth
  • High speed data synchronizer which minimizes circuitry
    Patent number: 4617480
    Abstract: A data synchronizer circuit which utilizes a CMOS process is provided. The synchronizer asynchronously receives input data and synchronizes the data to a predetermined clock signal. The synchronizer minimizes circuitry to provide fast operation and minimum latency between input and output terminals.
    Type: Grant
    Filed: October 22, 1984
    Date of Patent: October 14, 1986
    Assignee: Motorola, Inc.
    Inventor: Kenneth K. Au
  • Programmable edge defined output buffer
    Patent number: 4616147
    Abstract: A programmable edge defined output buffer clocks a first logic state to a first node when an input signal is in a first condition and a second logic state to a second node when the input signal is in a second condition. A programmable coupling circuit is programmable to couple the first and second nodes to an input of an amplifier. The programming selection determines in response to which signals will the first and second nodes be coupled to the input of the amplifier.
    Type: Grant
    Filed: November 15, 1984
    Date of Patent: October 7, 1986
    Assignee: Motorola, Inc.
    Inventor: Joseph Pumo
  • Address transition pulse circuit
    Patent number: 4614883
    Abstract: A circuit for generating a pulse in response to an address transition using an input NOR gate to initiate the generation of the pulse. A delay circuit provides a delayed signal for actively terminating the pulse after a predetermined time period. An inhibit circuit is used to prevent the delayed signal from attempting to actively terminate the pulse when there has been another address transition, thereby saving power.
    Type: Grant
    Filed: December 1, 1983
    Date of Patent: September 30, 1986
    Assignee: Motorola, Inc.
    Inventors: Lal C. Sood, James S. Golab, Armando L. DeJesus
  • MOS current limiting output circuit
    Patent number: 4612497
    Abstract: An MOS current limit circuit which provides current limiting protection is provided. A driver transistor of a conventional output stage is coupled to a current limiting transistor which is one transistor of a current mirror. The current limiting transistor of the current mirror has the V.sub.GS thereof accurately biased to insure a precise current limit value. When the current limiting transistor is not performing a current limiting function, the current limiting transistor is made conductive and further provides high voltage protection to the driver transistor when the driver transistor is nonconductive.
    Type: Grant
    Filed: September 13, 1985
    Date of Patent: September 16, 1986
    Assignee: Motorola, Inc.
    Inventor: Richard W. Ulmer
  • High speed input buffer having substrate biasing to increase the transistor threshold voltage for level shifting
    Patent number: 4612461
    Abstract: An input buffer which can be used as a TTL to CMOS input buffer in a CMOS integrated circuit has a CMOS input inverter for receiving an external input signal. The typical threshold voltage of the P and N channel transistors is relatively low for high speed operation. At least one of the P and N channel transistors of the input inverter has the magnitude of its threshold voltage increased by applying appropriate back bias voltage in the well in which it resides.
    Type: Grant
    Filed: February 9, 1984
    Date of Patent: September 16, 1986
    Assignee: Motorola, Inc.
    Inventor: Lal C. Sood
  • Method and apparatus for implementing an algorithm associated with stored information
    Patent number: 4607331
    Abstract: A circuit and method for implementing a predetermined data replacement algorithm associated with a fast, low capacity cache, such as least recently used (LRU), which is fast and which minimizes circuitry is provided. A latch stores the present status of the replacement algorithm, and an address control signal indicates which one of n sets of stored information in the cache has been most recently accessed, where n is an integer. The predetermined algorithm is implemented by a predetermined permutation table stored in a translator which provides an output signal in response to both the present status of the replacement algorithm and the address control signal. The output signal indicates which one of the n sets of stored information in the cache may be replaced with new information.
    Type: Grant
    Filed: May 13, 1983
    Date of Patent: August 19, 1986
    Assignee: Motorola, Inc.
    Inventors: Edgar R. Goodrich, Jr., Douglas R. Kraft
  • Switched capacitor precision difference amplifier
    Patent number: 4604584
    Abstract: A circuit which can selectively sample and hold two real time input voltages and provide an output voltage indicating the difference value of the input voltages is provided. A switched capacitor structure which provides no parasitic capacitance output error component when the two input voltages are substantially equal is used.
    Type: Grant
    Filed: June 10, 1985
    Date of Patent: August 5, 1986
    Assignee: Motorola, Inc.
    Inventor: Stephen H. Kelley
  • Bus master capable of relinquishing bus on request and retrying bus cycle
    Patent number: 4602327
    Abstract: A bus master is provided with the capability to accept a data transfer task from a CPU, which includes the performance of a predetermined sequence of data transfer operations between memory and a selected peripheral controlled by a respective controller. During any one of the operations, the bus master may be requested to relinquish the bus so that a higher priority transfer may occur or a deadlock condition resolved. In response to such request, the bus master immediately terminates the current bus cycle, but remembers the state thereof at the time of relinquishment. After the high priority transfer is completed, the bus master may be allowed to rearbitrate for use of the bus. Upon again obtaining control of the bus, the bus master restarts the bus cycle which was prematurely terminated and continues the sequence of operations as if no relinquishment had occurred.
    Type: Grant
    Filed: July 28, 1983
    Date of Patent: July 22, 1986
    Assignee: Motorola, Inc.
    Inventors: William P. LaViolette, David S. Mothersole, John Zolnowsky
  • A/D Self-testing circuit
    Patent number: 4599604
    Abstract: An A/D system having a capacitive DAC is provided with a circuit for accurately testing the functionality of the A/D system. An accurate reference voltage which is associated with A/D systems is utilized directly by selectively coupling the accurate reference voltage to predetermined ones of a plurality of rank ordered capacitors forming a binarily weighted DAC via a plurality of switches. After charging the predetermined capacitors, an effective test voltage results which is then coupled by the switches to successive approximation circuitry associated with the A/D system. A resulting digital output code may be compared with the weighted analog value of the switched reference voltage to test whether the circuitry of the A/D system is functioning properly.
    Type: Grant
    Filed: August 27, 1984
    Date of Patent: July 8, 1986
    Assignee: Motorola, Inc.
    Inventors: James A. McKenzie, Joe W. Peterson
  • Circuit for equalizing bit lines in a ROM
    Patent number: 4594689
    Abstract: A non-volatile memory has a plurality of coupling transistors for coupling bit lines to an equalization line in response to an equalization pulse. The equalization line has capacitance as do the bit lines. Prior to the occurrence of the equalization pulse, the unselected bit lines are charged to a first predetermined voltage, and the equalization line is charged to a second predetermined voltage by a high impedance reference voltage generator. A pulse generator provides the equalization pulse in response to an address transition.
    Type: Grant
    Filed: September 4, 1984
    Date of Patent: June 10, 1986
    Assignee: Motorola, Inc.
    Inventor: William J. Donoghue
  • High speed limited distance multiplexed data communications modem using a single twisted pair of conductors
    Patent number: 4594707
    Abstract: A multiplexed data communications modem providing high speed data communication via a single twisted pair of conductors having a distance up to two kilometers between a plurality of data terminals and remote communications equipment is provided. A burst mode ping-pong transmission scheme is utilized. A control portion selectively multiplexes data from each data terminal, and the variation of actual data rate of each data terminal has no effect on channel capacity of the other multiplexed data channels. A plurality of data interface circuits provides an asynchronous/synchronous interface between the multiplexed data terminals and a synchronous transceiver.
    Type: Grant
    Filed: September 17, 1984
    Date of Patent: June 10, 1986
    Assignee: Motorola, Inc.
    Inventors: John W. Merritt, Henry Wurzburg, Stephen H. Kelley
  • TTL to CMOS input buffer
    Patent number: 4593212
    Abstract: A TTL to CMOS input buffer has a CMOS inverter for receiving the TTL signal on its input. The inverter has a P channel transistor coupled between VDD and the output of the inverter, which has relatively low gain so that there is very little current flow through the inverter when the TTL signal is at low voltage logic high. A switch is coupled between VDD and the output of the inverter. The switch couples VDD to the output of the inverter in response to the TTL signal switching from a logic high to a logic low.
    Type: Grant
    Filed: December 28, 1984
    Date of Patent: June 3, 1986
    Assignee: Motorola, Inc.
    Inventor: Yehuda Svager
  • Parallel roller tool for unloading semiconductor device sockets
    Patent number: 4589201
    Abstract: A parallel roller tool for quickly and carefully unloading groups of semiconductor devices from spring-biased semiconductor device sockets. The parallel roller tool has a plurality of roller support plates which support the rollers and may serve to align them with various socket rows. Use of this roller tool permits rapid unloading of trays containing semiconductor devices without overstressing the trays or touching the semiconductor devices with the tool.
    Type: Grant
    Filed: April 17, 1985
    Date of Patent: May 20, 1986
    Assignee: Motorola, Inc.
    Inventors: Carlos A. Kissinger, Raun L. Goode
  • Precision triangle waveform generator
    Patent number: 4585951
    Abstract: A triangle waveform generator having precise edges is provided. A switched voltage controlled current source portion is coupled to an integrator circuit for providing the triangular output waveform. A switched capacitor integrator portion accurately controls the switched current source portion in response to both a reference voltage and the output voltage.
    Type: Grant
    Filed: October 24, 1983
    Date of Patent: April 29, 1986
    Assignee: Motorola, Inc.
    Inventor: Henry Wurzburg
  • Method and apparatus for a compare and swap instruction
    Patent number: 4584640
    Abstract: In a data processing system having linked lists it is useful to be able to add and delete items from such lists while maintaining the integrity of the linked nature of such lists. A new compare and swap instruction provides for effectively simultaneously swapping 2 values which is useful for safely adding and deleting items from linked lists. Prior to the instruction the status of the two value are read at the locations to be swapped. During the instruction these locations are checked again to ensure that no change has occurred at these locations before the instruction performs the swap of the two new values. The instruction then performs the proposed 2 value swap but only if no change has occurred at these two locations where the swap is to be performed.
    Type: Grant
    Filed: June 27, 1984
    Date of Patent: April 22, 1986
    Assignee: Motorola, Inc.
    Inventors: Douglas MacGregor, David S. Mothersole, John Zolnowsky