Abstract: An n-bit adder circuit, where n is an integer, for providing carry select addition of two input numbers is provided. A rank ordered plurality of section adders each have a plurality of full adders. Each full adder utilizes a single half adder to provide two sum bits which are coupled to a multiplexer which is an integral part of each section adder. One sum is for a carry-in and the other sum is for no carry-in. A method of minimizing logic circuitry which provides carry bits and carry sum select bits is provided. The carry bits and carry sum select bits control which of the two sums are provided by each section adder. By providing the carry bits and carry sum select bits in complement form every other order of section adder, logic circuitry and logic gate delays are minimized.

Abstract: A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.

Abstract: A switched capacitor comparator having two or more stages of differential input operational amplifiers utilizing sequentially switched feedback portions and feedback capacitors is provided. The use of feedback capacitors in a sequentially switched comparator provides accurate gain and stability. To further reduce offset voltage errors, a solid state transmission gate having a low "on" resistance is disclosed. A transmission gate having capacitors for partially compensating parasitic capacitance effects, a P-channel device and an N-channel device with a switched tub or substrate is provided to compensate parasitic capacitance effects. When the transmission gate is conducting, the tub or substrate of the N-channel device is switched from one of its current electrodes to a reference potential such as ground. Before the transmission gate is opened electrically, a settling time is provided to allow charge which is coupled from parasitic capacitance to settle.

Abstract: A voltage detecting circuit is disclosed having a first field effect transistor of a first type coupled in series with a second field effect transistor of a second type between a first supply voltage node and an input node, with the current channel regions coupled to the same node as the sources thereof, and the gates thereof coupled to a second supply voltage node. If the on resistance of the second transistor is significantly greater than that of the first transistor, the output node, formed by the common drains of the transistors, will be substantially the first supply voltage when the input signal is absent, and the voltage of the input signal signal when the latter is present.

Abstract: A memory circuit, having an array with adjacent side-by-side portions, has half of the array precharged by precharging alternate portions. Pairs of adjacent portions have common sense amplifiers which receive signals from only the precharged portion of the pair of adjacent portions. The sense amplifiers are then arranged so that the conductor lines to the output pads are uninterrupted.

Abstract: A code conversion circuit comprising logic for converting an n-bit binary number having a sign bit in two's complement code to sign-magnitude code is provided where n is an integer. The logic identifies whether or not the binary number is positive or negative. Regardless of polarity, the sign bit and least significant bit are directly outputted. If the binary number is positive, all bits are outputted with unchanged logic states. If the binary number is negative, the least significant bit of the n magnitude bits which has a logic one value is identified. The remaining n magnitude bits of higher significance are inverted and outputted with the other magnitude bits.

Abstract: A control state sequencer for controlling the execution of instructions of a microprocessor uses a PLA and a ROM to detect the current control state and instruction being processed by a processing unit and to provide the next control state of the instruction to the processing unit. An initial-state PLA and initial-state ROM detect when a new instruction is to be processed by the processing unit and provides the initial clock state of the new instruction to the processing unit.

Abstract: A digital to analog converter which provides positive and negative analog output signals in response to a digital input number is disclosed. The input number has n bits including a sign bit and n-1 magnitude bits, where n is an integer. An input receives the n-1 magnitude bits and is coupled to switches for selectively coupling a predetermined reference voltage to a capacitance portion comprising a rank ordered plurality of capacitors. First and second charges related to first and second portions of said n-1 magnitude bits, respectively, are sequentially integrated with respect to time by an integrator which is selectively coupled to the capacitance portion to provide an analog output signal. A buffer output amplifier selectively samples and holds the analog output signal.

Abstract: An amplifier circuit minimizes output voltage transients during powering up of the circuit. First and second bias current source portions are coupled to an input portion for receiving an input voltage. An amplifier portion is coupled to the input portion. The first bias current source portion provides a constant minimal current to the input portion which maintains the circuit bias voltage to the amplifier portion at near quiescent operating conditions. The second bias current source portion is switched to the input portion in response to a power control signal and provides bias current to the input portion necessary for circuit operation.

Abstract: A prescaler circuit which provides an output signal which is synchronous with and proportional in frequency to a clock signal is provided. A counter portion counts a predetermined number of cycles of the clock signal and provides a plurality of count signals after a predetermined number of clock signal cycles. A decoder portion is coupled to the counter portion and couples a reference voltage node to a decoder output in response to both an input control signal and the count signals. A latch portion is coupled to the decoder portion for holding the decoder output, and a delay portion is utilized to provide the scaled output signal after a predetermined amount of time delay. The prescaler utilizes both odd and even scaling factors.

Abstract: A single input oscillator circuit which provides an oscillating output signal in response to the presence of an input signal is provided. A differential comparator stage having a predetermined trip point established by a reference voltage is connected between the input terminal and a set-reset latch circuit. A gain stage has an input connected to the input termial, and variable bias is derived from both the differential stage and a set-reset latch circuit for providing the output signal in response to the voltage level of the input signal. A discharge portion is connected to the input terminal to periodically couple the input terminal to a voltage potential node in response to the latch circuit.

Abstract: A gate array which has power bus routing for increasing current availability to a plurality of transistor cells is provided. The gate array also has separate power busses for input/internal logic and output circuits. The gate array comprises n columns of transistor cells with two power busses extending substantially along each column to power the cells. Input/internal logic power busses and separate output power busses extend around the perimeter of the columns of transistor cells. At least one power strip for increasing current availability to the transistor cells is routed across the transistor cells substantially perpendicular to the n columns and is connected to both the power busses of each column and to the input/internal logic power busses.

Abstract: A method and apparatus for obtaining small fractional units of capacitance in amplifier circuits using units of capacitance which may be accurately ratioed is provided. Several embodiments are disclosed in which an input voltage is sampled onto two input capacitances with an opposite charge polarity. The two input capacitances are assigned capacitive values so that the second capacitive value is a fractional percentage of the first capacitive value. However, the effective total input capacitance is made to appear to be equal to the differential capacitive value which may be made a small fractional unit of capacitance.

Abstract: An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.

Abstract: An input buffer circuit having a single input for receiving input voltages characterized by having varying voltage swings is provided. First and second inverter circuits having differing switchpoint voltages are coupled to a level shifting position. The level shifting portion varies the level of swing of the input voltage and buffers the input voltage. In one form, voltage coupling circuitry is interposed between the level shifting portion and a latching portion which provides the input voltage as an output signal at a predetermined voltage level. In another form, voltage coupling circuitry controlled by control circuitry couples the output of the level shifting portion to an output in response to the input voltage.

Abstract: A multi-page ROM uses programmable pointers for selection of a page. The pointers each have a preliminary latch circuit, an output latch circuit, and a delay circuit. The preliminary latch circuit receives and stores program address signals when a first signal is present. The output latch receives the address stored in the preliminary latch when a second signal is present. The delay circuit removes the first signal before the second signal is present and delays the presence of the first signal for a delay period following the removal of the second signal.

Abstract: A frequency to voltage converter is described which utilizes an operational amplifier connected as a damped integrator and having a switched capacitive input and feedback element. If the capacitors are equal in size, the output voltage is a function of the ratio of the switching frequencies of the switched capacitors.

Abstract: A voltage reference circuit is disclosed having a common gate differential stage which utilizes the base-to-emitter voltage V.sub.BE, of a bipolar transistor to provide a reference current through a first resistor. Current mirror means are coupled to the differential stage to couple the reference current to second and third resistors which develop the output reference voltage. By ratioing the second and third resistors to the first resistor, a stable output reference voltage which is proportional to the V.sub.BE of the bipolar transistor is provided.

Abstract: A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.

Abstract: A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without static current flow when the TTL is a logic "1" by isolating the input from an input P channel transistor and using feedback from an input N channel transistor to turn off the P channel transistor. A second P channel transistor is used to couple a positive power supply voltage to the input P channel transistor in response to an output from the N channel transistor.