Abstract: Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

Abstract: Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M?1) and 2(M?1)?1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.

Abstract: Decryption keys used in decrypting encrypted configuration data for a programmable logic device are erased following decryption of encrypted configuration data. A self-erasing key memory delivers a decryption key to a programmable logic device and then automatically erases itself. The keys are then no longer available outside the programmable logic device.

Abstract: Described are methods and systems for encrypting and decrypting configuration data for programmable logic devices. An encrypted bitstream of configuration data includes two or more portions, each of which may be encrypted using a different key. Prior to loading, the author of each portion calculates the byte count for his or her portion and loads the required decryption key and byte count into a key and count memory. The designs are then loaded together as a single bitstream. The PLD decrypts the first portions using the first password. At the start of the partial bitstream, configuration logic loads the count associated with the decryption key for the first portions into a decrementing counter. The counter then decrements for each byte decrypted, reaching a count of zero when the first portion is fully decrypted. The configuration logic then selects the subsequent decryption key and associated count for the next portion of the bitstream.

Abstract: Described are programmable logic devices that decrypt proprietary configuration data using on-chip decryption keys. The keys are stored in a key memory that can be operated in a secure mode or a non-secure mode. The non-secure mode allows the decryption keys to be read or written freely; the secure mode bars read and write access to the decryption keys. The programmable logic device supports secure and non-secure modes on a key-by-key basis, allowing users to write, verify, and erase individual keys without affecting others.

Abstract: An asynchronous FIFO buffer communicates data between first and second clock domains. The FIFO buffer includes a shift register that accepts and shifts out data at a relatively high output frequency required for the second clock domain. The input data is loaded into the shift register in synchronization with the output clock; input data is not loaded into the shift register on each cycle of the output clock, however, because the input clock is slower than the output clock. A clock comparison circuit compares the input and output clocks and tracks the history of data transfers into the shift register to determine whether a given input datum should be loaded into the shift register during a given period of the output clock. The clock comparison circuit writes input datum into the shift register periodically, skipping write cycles as necessary so that input and output data rates match.

Abstract: A method is disclosed for redeploying an FPGA that has been restricted for use with a first design. The FPGA accepts only those configuration bitstreams whose CRC checksums match a value stored on the FPGA. The restricted FPGA is used with a second configuration bitstream for a second design by altering the second configuration bitstream so that it generates a CRC checksum that matches the value stored on the FPGA. The first checksum is derived by applying a CRC hash function to the first configuration bitstream. The second configuration bitstream is altered so that the second checksum generated when the CRC hash function is applied to the altered second configuration bitstream is identical to the first checksum. Altering the second configuration bitstream can result in an altered second configuration bitstream that is either longer than or the same length as the second configuration bitstream.

Abstract: Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of “nanotechnology” and molecular-scale technology, or “molectronics.” Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.

Abstract: Described are methods and circuits that allow encrypted and unencrypted, or differently encrypted, configuration data to define the contents of the same physical memory frame or frames within a programmable logic device.

Abstract: Described are various methods and systems for encrypting/decrypting configuration data for programmable logic devices. In configuration data defining a number of separately encrypted subdesigns, or “cores,” each subdesign includes a shared password or a unique authentication code to ensure the designs belong together. Other embodiments prohibit the overwriting of configuration memory to prevent the inclusion of unauthorized designs. Still other embodiments protect key secrecy while enabling users to read, write, and verify the keys.

Abstract: Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.

Abstract: Described are various methods and systems for protecting proprietary configuration data for programmable logic devices. In one example, frames of configuration memory include overwrite-protect circuitry that reduces the risks associated with Trojan Horse attacks by preventing the overwriting of frames between device resets.

Abstract: Described are small, efficient SRAM cells that are insensitive to read errors. SRAM cells in accordance with one embodiment include a pair of cross-coupled inverters extending between first and second bit nodes and a read amplifier extending from one of the first and second bit nodes to an associated bitline. During a read access to a given memory cell, the corresponding read amplifier isolates the bit nodes from the bitlines to prevent the voltage on bitline BL from disturbing data stored in the memory cell.

Abstract: Described are programmable logic devices with configuration memory cells that function both as RAM and ROM. A PLD incorporating these memory cells to store configuration data can be mask-programmed with a customer design, rendering the PLD an application-specific integrated circuit (ASIC). The mask programming can be selectively disabled, in which case each configuration memory cell behaves as a static, random-access memory (SRAM) bit. In this mode, a PLD employing these dual-mode memory cells behaves as a reprogrammable PLD, and can therefore be tested using generic test procedures developed for the PLD. The dual-mode memory cells thus eliminate the burdensome task of developing application-specific test procedures for designs ported from a PLD. As an added benefit, in the ROM mode these memory cells are not susceptible to radiation-induced upsets, so for example, PLDs incorporating these memory cells are better suited for aerospace applications than conventional SRAM-based PLDs.

Abstract: Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.

Abstract: Described is a power multiplexer that alternately transmits zero, supply voltage, and a relatively high voltage to a common output node. The power multiplexer includes low-impedance voltage switches, at least one of which includes a well-voltage select circuit. The well-voltage select circuit adjusts the well bias on a power-switching transistor, and consequently protects the power-switching transistor from damage caused by gate breakdown and forwarding biasing of the well.

Abstract: Described are methods and circuits of programming a programmable logic device with encrypted configuration data using one or more secure decryption keys. Configurable resources within PLDS in accordance with one embodiment are divided into first and second collections of configurable interconnect resources separated by a collection of switches. One collection of resources has access to one or more decryption keys required to decrypt the encrypted configuration data. The switches protect the proprietary keys by providing a secure boundary around the portion granted key access during the decryption process. Closing the switches after configuration clears user memory to prevent users from accessing stored versions of the proprietary keys.

Abstract: Disclosed is apparatus to enhance thermal energy transfer from a heater to a DUT in IC handler systems. The pick-up head of an IC handler system is made of metal blocks in maximal thermal contact, and further includes an electrically resistive and thermally conductive layer. The electrically resistive layer provides ESD protection to the DUT. The preferred apparatus uses a collapsible billows suction cup to secure, pick-up, and align DUTs.