Abstract: A method and apparatus for implementing fast sum-of-products logic in a field programmable gate array (FPGA) is disclosed. The method includes literal-sharing decomposition of the sum-of-products logic to reduce the number of configurable logic block (CLB) slices required to implement wide fan-in logic functions on an FPGA. The decomposition is performed by combining product terms having similar literal patterns. The apparatus includes a CLB including a plurality of slices and a second-level logic (separate from the slices) circuit to combine the outputs of the slices. Typically, the second-level logic is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of the slice with the output of another slice preceding the first slice.

Abstract: Described are glitchless clock control circuits capable of switching away from a failed clock. One embodiment supports three basic functions: clock select, clock enable, and clock ignore. The clock-select function provides a selected one of a plurality of clock signals on a clock-distribution node. The select signals used to switch between clock signals need to be synchronous with any of the clock signals. The clock-enable function allows the clock control circuit to synchronously block or pass a selected clock signal. Finally, the clock-ignore function allows the clock control circuit to ignore a selected clock if necessary, for example, to switch away from a failed clock.

Abstract: A bridge circuit disposed between a device under test (DUT) and conventional automatic test equipment (ATE) extends the performance of the ATE. The bridge circuit allows the ATE to test ICs capable of operating at frequencies above the ATE's normal performance limits. In some embodiments, the bridge circuit also extends ATE functionality, providing frame alignment and automatic test-vector generation, for example, and can increase the number of available test channels.

Abstract: Test methods and circuits isolate thermal effects from AC effects on circuit performance. Critical paths for a failing programmable logic device (PLD) are identified and tested. This testing minimizes the impact of power-supply flicker and noise by eliminating or inactivating circuitry not required to test the critical paths. DC thermal energy generators are instantiated on the PLD adjacent the critical paths to heat the critical paths to one or more test temperatures. The critical paths are then tested over an appropriate range of temperatures and supply-voltages.

Abstract: A tunable narrow-band filter that includes a sigma-delta modulator. In one embodiment, a conventional DC canceler is modified to include a re-quantizer in the feedback loop in the form of a ?? modulator. In another embodiment, a digital receiver employs a processing chip, such as an FPGA, that includes a ?? modulator to requantize oversampled control signals in the digital receiver. In still another embodiment, a wide-bandwidth sigma-delta loop has a tunable center frequency.

Abstract: A clock control circuit routes one of a plurality of clock signals to a clock output node, and employs an asynchronous state machine to switch between clock signals without introducing glitches. To switch from a first to a second clock, the control circuit samples the logic level of the first clock signal to obtain a sampled logic level. The control circuit then provides a constant version of the sampled logic level on the clock output terminal until the second clock signal transitions to the sampled logic level, at which point the control circuit routes the second clock signal to the clock output node.

Abstract: Described are circuits and methods for aligning data and clock signals. Circuits in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

Abstract: Described are methods for accurately measuring the skew of clock distribution networks on programmable logic devices. Clock distribution networks are modeled using a sequence of oscillators formed on the device using configurable logic. Each oscillator includes a portion of the network, and consequently oscillates at a frequency that depends on the signal propagation delay associated with the included portion of the network. The various oscillator configurations are defined mathematically as the sum of a series of delays, with the period of each oscillator representing the sum. The respective equations of the oscillators are combined to solve for the delay contribution of the included portion of the clock network. The delay associated with the included portion of the clock network can be combined with similar measurements for other portions of the clock network to more completely describe the network.

Abstract: A test oscillator circuit separately measures the signal propagation delay for both rising and falling edges through one or more multi-input combinatorial logic circuits. A number of components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component passes signal edges to a subsequent component in the ring, so the oscillator produces an oscillating test signal in which the period relates to the delays through the components. In some embodiments, the multi-input combinatorial logic circuits emulate tri-state buffers. These embodiments characterize the speed at which these logic circuits enable and disable signal paths.

Abstract: Disclosed is a DC thermal energy generator for heating localized regions of an integrated circuit. The integrated circuit includes a pair of static circuits whose outputs are shorted, and are in contention. Contention causes current to flow through the circuits, generating heat. Integrated-circuit temperatures can be varied by turning on more or fewer thermals energy generators. The thermal resistance of a, packaged integrated circuit is computed using a well-known relationship integrated circuit's measured temperature, power consumption, and the ambient temperature.

Abstract: A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Abstract: Described are clips for collecting sensors into multi-sensor arrays for insertion into well and the like. The clips are adapted to easily receive the sensors and provide a lock for securing the sensors once installed. The clips can be adapted for use with elements other than sensors, in particular for applications in which a number of relatively elongated members are to be secured in parallel.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: Described is a photolithography “deep-well lithography” process for forming Micro-Electro-Mechanical Systems (MEMS) structures. The process differs from conventional lithography in that the surface being patterned is not the uppermost surface, but is instead the bottom of a “well” defined beneath the uppermost surface. The focal plane of the photolithography equipment is offset from the uppermost surface as appropriate to account for the depth of the well in which the pattern is to be formed. The bottom of the well is then patterned to produce a desired structure.

Abstract: Described are modular water sensors designed to speed assembly and otherwise improve manufacturability. Various sensors, modules, and cables communicate via connector systems that employ elastomeric conductors to establish and maintain electrical contact between perpendicular wiring-board surfaces. The elastomeric conductors are held in place using easily assembled systems of clips and retainers.

Abstract: Described are methods and circuits for aligning data and clock signals. Methods in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

Abstract: A mail server collects messages from a number of user accounts and presents them to the user from a single location. The user can set the mail server to block unwanted messages and to forward others to various receiving devices, including mobile telephones and pagers. Forwarded messages are automatically reformatted for the receiving device, while a copy of the original message is retained. The retained copy can be viewed later if the user is interested in message content that was not available to the wireless device. The user can also use the wireless device to forward the original message to another receiving device. In the case of forwarding, the saved original message and not the reformatted message is sent to the forwarding address. Some embodiments include an email agent that automatically pushes messages from intranet clients to the mail server through a firewall, thereby enabling the mail server to consolidate messages from intranet and Internet sources.

Abstract: A processor includes a translation look-aside buffer (TLB) that relates virtual page addresses to both physical page addresses and main-memory addresses. If the processor references a virtual page address in the TLB for which there is no corresponding information in cache, the processor passes the main-memory address directly to main memory, avoiding the latency normally associated with systems that translate a physical page address to a main-memory address before accessing information from main memory.

Abstract: Described are memory systems designed to emphasize differences between memory-cell access times. As a consequence of these access-time variations, data read from different memory cells arrives at some modified output circuitry. The output circuitry sequentially offloads the data in the order of arrival. Data access times are reduced because the output circuitry can begin shifting the first data to arrive before the slower data is ready for capture. Differences between data access times for cells in a given memory array may be emphasized using differently sized sense amplifiers, routing, or both.

Abstract: A clock distribution circuit and method in which the incoming clock frequency is divided by two to create a reduced-frequency global clock signal. A dual-edge-correcting clock synchronization circuit aligns both the rising and falling edges of the global clock signal to separately to nullify the clock-distribution errors associated with rising and falling clock edges.