Abstract: Described are a method and circuit for time-multiplexing two or more PLDS. The invention allows a pair of PLDs to sequentially perform more than two logic functions. The PLDs share common input and output nodes. The output nodes of each PLD may be tri-stated so that either PLD can be active (i.e., perform some logic function) at any given instant without logic conflicts on the common output nodes. A configurable-logic modification (CLM) circuit determines which PLD is active. The CLM circuit can selectively modify the logical configuration of one PLD while the other PLD actively performs some logical operation and provides the result of that logical operation on the common output nodes. The CLM circuit can then deactivate the active PLD and activate the newly configured second PLD to implement the second logic function.

Abstract: Described are dynamic memory cells for use in FPGAs. Each memory cell includes a dynamic memory element that occupies less chip area than conventional static memory elements and that can be implemented using standard CMOS processes. In one embodiment, a conventional access transistor is connected to a pass transistor via a CMOS inverter. The CMOS inverter includes a pair of complementary MOS transistors sharing a common gate connection, and therefore exhibiting a combined gate capacitance. This gate capacitance at the input of the inverter supplements or replaces the capacitor normally required in conventional dynamic memory cells. Another embodiment uses the parasitic gate capacitance of a pass transistor for dynamic data storage. This embodiment requires that the voltage levels on the source and drain of the pass transistor be controlled during write and refresh operations to ensure that the gate capacitance of pass transistor stores an appropriate level of charge.

Abstract: An antifuse is described that can be formed without masks or mask steps beyond those required for a conventional CMOS process. The antifuse includes adjacent p-type and n-type diffusion regions that together form a P-N junction. The diffusion regions are tapered toward one another such that the P-N junction is located at a necked-down region of the antifuse. The diffusion regions are connected to respective terminals of a programming-voltage source via first and second metal electrical contacts, typically of aluminum metal. Each of the first and second electrical contacts includes a point directed toward the other of the first and second electrical contacts. The antifuse is programmed by providing a reverse-bias programming voltage across the electrical contacts. This programming voltage exceeds the breakdown voltage of the P-N junction so that current flows through the necked-down region of the antifuse between the points on the respective first and second electrical contacts.

Abstract: A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

Abstract: A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

Abstract: A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.