Patents Represented by Attorney Arthur W. Fisher
  • Patent number: 5774719
    Abstract: A method in accordance with the invention involves the normalization of a C language-type data structure received by a process in a distributed computing environment (DCE) to ensure that padding bits are consistently used. The method steps may advantageously be performed by a client process prior to and subsequent to a remote procedure call (RPC) to ensure that the padding bits are not undesirably changed as a result of the RPC. The method steps can also be performed by a server process to ensure that the structures it receives in RPCs are consistent in their use of padding bits. Normalization of the data structure permits a memcmp( ) or similar comparison function to be used to compare data structures without the risk that dissimilar padding bits will result in a false negative from the comparison.
    Type: Grant
    Filed: January 8, 1993
    Date of Patent: June 30, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Steven J. Bowen
  • Patent number: 5774727
    Abstract: A language construct that allows a software programmer to use an intermediate or high-level language command to explicitly group operations or fuse loops in a group of statements operating on parallel arrays is disclosed. The command instructs a compiler, which would otherwise add temporary variables to avoid data dependencies or perform data dependency analysis, to translate the enclosed statements directly into machine language code without adding those temporary variables and without performing any data dependency analysis. Execution of the command results in the performance of the group of statements by all of the virtual processors.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: June 30, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Robert J. Walsh, Bradley Miller
  • Patent number: 5765193
    Abstract: A data storage system includes a multi-tasking processor which manages a write cache to identify adjacent blocks held in the write cache which are to be included in a next write operation, while at the same time handling data transfer requests from a system host. The processor monitors the write cache and when the cache has fewer than a predetermined number of storage locations free, initiates a block-merge task. The processor then determines which block in the write cache is least recently used and, based on virtual block numbers assigned to the data blocks, identifies the blocks in the write cache which are adjacent to the least recently used block and are within the same chunk as that block. The processor maintains a list of these adjacent blocks and the locations in which the blocks are held in the write cache.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: June 9, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Mitchell N. Rosich, Eric S. Noya, Jeffrey T. Wong
  • Patent number: 5764877
    Abstract: Modern database systems provide media recovery by taking periodic backups and applying a transaction log to the backup to bring the data up-to-date. A multi-versioned database is one that retains and provides access to historical versions of data. The present invention shows how a history database, supported by the Time-Split B-tree, can be used to also provide the backup function of media recovery. Thus, the same versions used for database history are used for database backup. The cost of taking a backup is comparable to the cost of a good differential backup method, whereby only changed data is backed up. The media recovery cost, especially when the media failure is only partial, e.g., a single disk page, will frequently be lower.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: June 9, 1998
    Assignee: Digital Equipment Corporation
    Inventors: David Lomet, Betty Salzberg
  • Patent number: 5764503
    Abstract: A method and apparatus for controlling the providing of conditioned AC power, with the conditioned AC power being capable of being provided on a continuous basis. Unconditioned AC voltage is received by transverters. The transverters convert the unconditioned AC voltage into a transverter AC output voltage. The transverter AC output voltage is monitored by current and voltage sensors. A transverter control signal is developed in response to changes in the current and voltage sensing in comparison with a reference signal. The transverter control signal then regulates conversion of the transverter AC output voltage into the desired conditioned AC output voltage. In multi-phase AC voltage systems conditioned AC voltages for each phase are provided.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: June 9, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Gerald J. Brand, Don L. Drinkwater, James M. Simonelli, Zeljko Arbanas
  • Patent number: 5761501
    Abstract: Disclosed herein is a stacked skip list data structure for maintaining select nodes on multiple lists. The data structure includes a primary and a secondary skip list of nodes. Each node in the primary skip list uses at least one forward pointer in a primary array of forward pointers and provides a node level field for storing the level of such node, the level determined by the number of pointers being used. A secondary skip list is stacked on the primary skip list of nodes. It includes a subset (zero or more nodes) occurring on the primary skip list and utilizes zero or more unused forward pointers in the primary array as its forward pointers. Thus, a system agent performing operations on the secondary skip list utilizes the node level in the node level field as an index into the primary array of forward pointers to locate the secondary array of forward pointers.
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: June 2, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Clark E. Lubbers, Susan G. Elkington
  • Patent number: 5761731
    Abstract: A mechanism for ensuring the accurate and timely completion of atomic transactions by multiple nodes coupled to a memory via a common interconnect in a multiprocessor system includes a plurality of nodes coupled to a bus, the plurality of nodes including memory nodes, I/O nodes, and processor nodes. The memory nodes are each apportioned into a plurality of banks and together comprise the memory. Associated with each bank is a busy signal, indicating the availability of the bank of memory for transactions. A node may issue an atomic transaction to a block of memory data through the use of READ.sub.-- BANK.sub.-- LOCK and WRITE.sub.-- BANK.sub.-- UNLOCK instructions. The node executing the atomic transaction monitors the state of the busy signals of the banks, and when the bank is available, the node issues a READ.sub.-- BANK.sub.-- LOCK instruction, which sets the busy bit to indicate the unavailability of the bank. Upon the completion of the READ.sub.-- BANK.sub.-- LOCK instruction, the node issues a WRITE.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: June 2, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Stephen R. Van Doren, Denis Foley, David M. Fenwick
  • Patent number: 5758778
    Abstract: A grain separator to separate and remove contaminants such as dust and debris from grain including an intermediate separator housing having a grain inlet port to receive grain to be scoured from an external source, a grain outlet port to feed scoured grain to an external collector, a first containments discharge port to discharge heavier contaminants removed from the grain to a first external receptacle and a second contaminants discharge port to discharge lighter contaminants removed from the grain to a second external receptacle, a mechanical separator and transport assembly operatively disposed within the intermediate separator housing to receive the grain and contaminants from the grain inlet port to separate the contaminants from the grain and to move the grain from the grain inlet port to the grain outlet port for collection in the external collector, a first containments transport assembly disposed to receive the heavier contaminants from the mechanical separator and transport assembly and to move the
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: June 2, 1998
    Inventor: Robert Kershner
  • Patent number: 5758106
    Abstract: A commander module including means for determining whether control of a system bus is required, means for requesting control of the system bus, prior to determining whether such control is required, and means, responsive to the determining means, for indicating that control of the system bus is required. A computer system including the system bus and at least two such commander modules coupled to the system bus and including means for arbitrating for control of the system bus including means for granting control of the system bus to one of the commander modules indicating that control of the system bus is required and having the highest arbitration priority among those commander modules also indicating that control of the system bus is required.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: May 26, 1998
    Assignee: Digital Equipment Corporation
    Inventors: David M. Fenwick, Denis Foley, Stephen R. Van Doren
  • Patent number: 5758183
    Abstract: Programs to be executed on a distributed computer system are instrumented to allow data sharing. The distributed computer system includes a plurality of workstations. Each workstation includes a processor, a memory having addresses, and an input/output interface connected to each other by a bus, the input/output interfaces connecting the workstations to each other by a network. A set of virtual addresses assigned to the memories are allocated to store a shared data structure as one or more blocks accessible by instructions of programs executing in any of the processors. The size of a particular allocated block can vary with the shared data structure. Each block includes an integer number of lines, and each line including a predetermined number of bytes. Prior to executing the programs, the programs are statically analyzed to locate instructions that access the shared data stored at target addresses of the lines of the one or more blocks.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: May 26, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Daniel J. Scales
  • Patent number: 5758142
    Abstract: A predictor which chooses between two or more predictors is described. The predictor includes a first component predictor which operates according to a first algorithm to produce a prediction of an action and a second component predictor which operates according to a second algorithm to produce a prediction of said action. The predictor also includes means, coupled to each of said first and second predictors, for choosing between predictions provided from said predictors to provide a prediction of the action from the predictor. The predictor can be used to predict outcomes of branches, cache hits, prefetched instruction sequences, and so forth.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: May 26, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Scott McFarling, Simon C. Steely, Jr., Joel Emer, Edward McLellan
  • Patent number: 5754860
    Abstract: Techniques used in testing software are described. A test generator produces a source program used to test two or more compilers using a differential testing technique. The test generator includes a grammar with added semantic constraints to minimize the generation of non-conforming source programs. The source program is a conforming source program conforming to constraints included in a programming language standard. By using properties of a conforming source code, a differential testing technique is described in which a test failure indicates that one or more of the compilers is not processing the source program correctly in accordance with the programming language standard. If a test failure is detected, the source program causing the test failure is reduced using various reduction and simplification techniques.
    Type: Grant
    Filed: July 23, 1996
    Date of Patent: May 19, 1998
    Assignee: Digital Equipment Corporation
    Inventors: William M. McKeeman, August C. Reinig, Andrew Payne
  • Patent number: 5754753
    Abstract: A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits - gate arrays - it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: May 19, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Donald Smelser
  • Patent number: 5753593
    Abstract: An environmentally compatible aquatic herbicidal composition comprising at least one surfactant and at least one high terepene containing natural oil to effectively control target aquatic vegetation including Red Azolla, Salvinia Molesta and Lemna.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: May 19, 1998
    Inventors: Erroll M. Pullen, Melvin D. Pullen
  • Patent number: 5751554
    Abstract: An integrated circuit handling, packaging and testing apparatus in the form of a testable chip carrier comprising a rigid substrate onto which a chip may be bonded, and which provides a high density interconnect pattern orthogonally aligned to the chip bond pads for wire bonding thereto. The interconnect also provides external bonding points patterned for similar orthogonal alignment to the external device to which the chip is to be connected, and the dimensions of the carrier are substantially smaller than an equivalent standard or custom package type. A hermetic or non-hermetic seal lidding operation may be carried out on the chip and carrier. The carrier also provides a detachable test perimeter allowing full-functional testing and burn-in of the attached wire-bonded chip prior to placement on a printed circuit board or multi-chip module.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: May 12, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Simon Mark Williams, Michael Lawrence McGeary
  • Patent number: 5745879
    Abstract: A distributed computer system employs a license management system to account for software product usage. A management policy having a variety of alternative styles and contexts is provided. Each licensed program upon start-up makes a call to a license server to check on whether usage is permitted, and the license server checks a database of the licenses, called product use authorizations, that it administers. If the particular use requested is permitted, a grant is returned to the requesting user node. The product use authorization is structured to define a license management policy allowing a variety of license alternatives by values called "style", "context", "duration" and "usage requirements determination method". The license administration may be delegated by the license server to a subsection of the organization, by creating another license management facility duplicating the main facility.
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: April 28, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Robert M. Wyman
  • Patent number: 5745900
    Abstract: A computer implemented method indexes duplicate information stored in records having different unique addresses in a database. A fingerprint is generated for each record, the fingerprint is a singular value derived from all of the information of the record. The fingerprint is stored in the index as a unique fingerprint if the fingerprint is different than a previously stored fingerprint of the index. A reference to the unique address of the record is stored with the fingerprint. If the fingerprint is identical to the previously stored fingerprint, then store the reference to the address of the record with the previously stored fingerprint.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: April 28, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Michael Burrows
  • Patent number: 5745696
    Abstract: In an interactive video-on-demand system, real-time programs are encoded as a transport stream including a plurality of transport stream packets. Some of the transport stream packets include timing signals indicating the real time of the program. The transport stream packets are formatted into transport cells for transport over an asynchronous transfer mode network from a source to a destination. The cells are transported at a transport rate which is determined by a network clock. The transport rate is chosen to deliver the transport stream faster than the real time of the program. While transporting the transport stream, it is determined if the transport stream is being transported ahead of the real time of the program. In this case, idle cells are injected into the transport stream to have the program arrive at the destination in the real time of the program.
    Type: Grant
    Filed: April 10, 1995
    Date of Patent: April 28, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Jeffrey B. Mendelson, Matthew S. Goldman, David E. Morris
  • Patent number: 5745899
    Abstract: An indexing method is provided for a database storing information as records at unique addresses. Pairs are generated for each record, each pair includes a word representing a portion of the information of the record and an associated location. The locations are assigned sequentially as the information is parsed into words. Pairs are also generated for attributes common to each record. In this case, each pair includes a metaword representing the attribute and the location of the last word of the record. Furthermore, two pairs are generated for one or more immediately adjacent words having a common attribute. Here, each pair includes the metaword representing the attribute. The location associated with the first of two pairs is the location of the first adjacent word, and the location of the second pair is the location the last adjacent word. The pairs are sorted first according to the words and metawords, and second according to the location assigned to the words.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: April 28, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Michael Burrows
  • Patent number: D395763
    Type: Grant
    Filed: June 2, 1997
    Date of Patent: July 7, 1998
    Inventor: Stephen R. Machell