Abstract: An apparatus for dithering an input image to produce an output array for representation on an output device is described. The apparatus includes an input device to store input image pixels having a first plurality of chrominance or luminance levels; a dithering system including a dither template including an M by N matrix of integer threshold values, the uniform distribution of threshold values throughout the dither template possessing homogeneous attributes. The apparatus further includes a normalizer unit for normalizing the threshold values of the dither template for storage in a dither matrix according to the first plurality of chrominance or luminance levels of the input image pixels and a second plurality of chrominance or luminance levels of the output array and a summation unit to add the input image pixel chrominance or luminance values to the normalized threshold values of the dither matrix.

Abstract: A computer implemented method for generating a compressed index of information. The information is stored as a plurality of records in a database. Indexable portions of information are sequentially parsed to generate words and metawords. The words represent the portions, and the metawords represent attributes of the portions. A location is sequentially assigned to each word and metaword in the order that the portions are parsed to form pairs. The pairs are sorted first according to the words and metawords, and second according to the locations. Index entries are written to a memory for each unique word and metaword. Each index entry includes a word entry or a metaword entry, and one or more location entries. The word and metaword entries use a prefix encoding which indicates the number of bytes that the unique word or metaword of a next index entry has in common with the unique word or metaword of a previous index entry. The location entries use a delta value encoding.

Abstract: In a computer implemented method, a plurality of records are stored in a database at unique record addresses. The information of each record is parsed into a set of individual words where each word represents a portion of the information of a particular record. A unique sequential location is assigned to each word so that the location of a first word of a next record sequentially follows the location of a last word of a previous record. Pairs are formed from the words and their assigned location. For attributes common to a particular record, generate a record metaword, and assign the location of the last word of the record to the metaword. For attributes common to subsets of words, generate a first and second field metaword, and assign the location of the first and last word of the subset to the first and second field metaword to form pairs.

Abstract: A computer implemented method performs constrained searching of an index of a database. The information of the database is stored as a plurality of records. A unique location is assigned to each indexable portion of information of the database. Index entries are written to a memory where each index entry includes a word entry representing a unique indexable portion of information, and one or more location entries for each occurrence of the unique indexable portion information. The index entries are sorted according to a collating order of the word entries, and sequentially according to the location entries of each index entry. A query is parsed to generate a first term and a second term related by an AND logical operator, the AND operator requires that a first index entry corresponding to the first term and a second index entry corresponding to the second term both have locations in the same record to satisfy a query.

Abstract: A method indexes a database so that records including literal values, and numeric values within a specified range can be located. The range is selected from an interval of values. Each record of the database is indexed by storing index entries in a memory. Each index entry includes a literal word entry representing a unique portion of information of the database, and one or more numeric location entries indicating occurrences of the portion of information. A plurality of sets of subintervals are generated from the numeric interval of values. Each set of subintervals includes all of the values of the interval. A first set includes one subinterval for each value of the interval, and each next set includes one interval for a group of adjacent subintervals of a previous set. The subinterval of the last set is the entire interval of numeric values. Each subinterval is represented by a unique literal which can be indexed as a word entry in the index.

Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.

Abstract: A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

Abstract: A method of managing faults in a computer system including the steps of detecting an error, handling the error along a functional hierarchy and, further, handling a fault that caused the error in a management hierarchy which can be operated separately from the functional hierarchy.

Abstract: Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction.

Abstract: A method of forming cobalt silicide on source/drain regions and polysilicon gate areas of an MOS integrated circuit uses an improved technique to prevent unwanted oxidation of cobalt or growth of silicide on other areas of device. A thin titanium nitride (or titanium tungsten) film is deposited on top of a cobalt film following the steps of patterning the polysilicon gate, source/drain implant and sidewall oxide spacer deposition and etch. The titanium nitride film allows formation of defect-free cobalt silicide during an elevated-temperature anneal. Without the titanium nitride film, the cobalt is likely to oxidize and/or form cobalt silicide in unwanted regions of the device, which can cause device failure.

Abstract: Methods and apparatus for facilitating the use of existing onsertion machines by trimming and sequencing a plurality of components to be onsetted on an as-needed basis from components of generic values obtained from the manufacturer and providing the sequence of components to a single pick-up point on the onsertion machine. Post-encapsulation trimming of these components by laser also results in novel components of high precision.

Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

Abstract: This invention packages option devices, such as floppy drives and hard disk drives, within an enclosure, thereby providing EMI/RFI shielding, promoting unimpeded option device electronic signaling, and reducing wasted space within an enclosure, such that small enclosures may encase the components. This invention includes a cage, for holding option devices, that is groundingly mounted in spaced relation to the major surface of a logic board, and an option device bracket that is slideably mounted within the cage. Each of the option device brackets contains one option device.

Abstract: A method and apparatus for bandwidth balancing of data transfer operations between a computer and a storage subsystem are disclosed. The storage subsystem contains a number of storage devices such as magnetic disk drives. Data to be stored is supplied by the computer to the storage subsystem in the form of a transfer unit through a communication channel. The storage subsystem divides the transfer unit into a number of stripes of a pre-determined size. Each stripe is allocated to a separate disk drive whose disk surfaces are formatted into a number of track bands. Each track band is composed of several contiguous tracks associated with the same data transfer rate. Each stripe is then stored on its disk drive within a selected track band. Both data storage and retrieval from each disk drive occur at the data transfer rate associated with the accessed track band.

Abstract: A system for controlling the transmission of cells from a network node over multiple Virtual Circuits (VCs) is disclosed. The system performs traffic shaping, as required by connection based systems such as Asynchronous Transfer Mode (ATM), for each VC connected with a network node, so that the Quality of Service (Qos) parameters established when the connection was established are not exceeded. The system includes a process for scheduling the transmission of cells from the network node. The scheduling process periodically scans a table having entries corresponding to virtual circuits connected with the network node. During each scan of the table, the scheduler increments a sustainable rate accumulator field and a peak rate accumulator field of each table entry that corresponds with a virtual circuit that is open, and for which there is a cell ready to be transmitted.

Abstract: The present invention includes an approach to index tree structure changes which provides high concurrency while being usable with many recovery schemes and with many varieties of index trees. The present invention permits multiple concurrent structure changes. In addition, all update activity and structure change activity above the data level executes in short independent atomic actions which do not impede normal database activity. Only data node splitting executes in the context of a database transaction. This feature makes the approach usable with the diverse recovery mechanisms, while only impacting concurrency in a modest way. Even this impact can be avoided by re-packaging the atomic actions, at the cost of requiring more from the recovery system.

Abstract: A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a clock distribution network of an integrated circuit (IC) chip. Delay measurement of the associated (IC) chips on the module is provided by sensing the clock signal at the beginning of the network and at the end of the network. The BEFORE and AFTER sense taps are routed to a signal generation circuit on the repeater chip where measurement signals are generated that define the beginning and end of a measurement cycle. A clock delay path circuit on the repeater chip contains the logic circuitry required to measure and compensate for the actual measured intrinsic propagation delays of the total clock transmission network.

Abstract: A computer system with multiple execution units operates by treating a logical program as a tree structure with segments which include several computer instructions. Segments of the tree structure are connected by nodes which represent decisional instructions in the logical program. Serial numbers are assigned to each instruction within each of the tree structure. The instructions and then rearranged into a set of instructions which are no longer linearly dependent. The original serial numbers assigned to each instruction are retained with the instructions after rearrangement. During rearrangement, path information is added to each instruction to indicate its commit point. The serial numbers and path information allow reconstruction of the original set of instructions from the rearranged set of instructions. The path codes represent a path through the tree structure to a particular one of the segments in which all of the instructions in the associated subset will be committed in logical terms.

Abstract: An electronic testing system can test an electronic device which has more signal pins or pads (i.e., contacts) than the maximum number of tester probes. The testing system connects the contacts to the tester such that groups of contacts share individual tester signal lines. The testing system uses special selector logic on the device to be tested to determine which particular contacts of the groups are "currently output active", or capable of transmitting data. At each step in the testing procedure, the system can vary the sets of contacts which are chosen to be currently output active, thereby resulting in a high percentage of the possible states of the device being tested.