Abstract: Various methods and systems for implementing a sectored least recently used (LRU) cache replacement algorithm are disclosed. Each set in an N-way set-associative cache is partitioned into several sectors that each include two or more of the N ways. Usage status indicators such as pointers show the relative usage status of the sectors in an associated set. For example, an LRU pointer may point to the LRU sector, an MRU pointer may point to the MRU sector, and so on. When a replacement is performed, a way within the LRU sector identified by the LRU pointer is filled.

Abstract: A system and method for improving the isolation and diagnosis of hardware faults in a computing system wherein means are provided for indicating whether unusable data has previously triggered diagnosis of the hardware fault that caused the data to be unusable. If diagnosis has not been performed, the flag is not set. If diagnosis has already been performed, the flag is set. One embodiment comprises an interface which is used to convey data from one subsystem to another. When the interface receives data from the first subsystem, the data is examined to determine whether it contains an uncorrectable error (including missing data.) If the data contains an uncorrectable error, the interface examines the flag corresponding to the data to determine whether hardware fault diagnosis has already been initiated. If diagnosis has already been initiated, the data is passed to the second subsystem without initiating further diagnosis.

Abstract: A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests for a memory interface and receiving requested data from the memory interface, comprises a data transfer initiating unit for outputting first address data identifying a first memory range. Further, a boundary alignment unit is provided for generating second address data using the first address data, where the second address data identifies a second memory range that differs from the first memory range in at least one boundary. Further a corresponding boundary alignment may be done in a receive DMA engine. The DMA mechanism may be performed in a USB-2 host controller that has HyperTransport capabilities.

Abstract: A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.

Abstract: An EMI reduction element and a protection element are provided with an electrical component. The electrical component has a distal end, and the EMI reduction element has a height and a distal side. The EMI reduction element is secured to the electrical component. The protection element includes a middle portion that has a maximum height. The maximum height is based on the height of the EMI reduction element, and is preferably about 30% to about 50% of the reduction element height. The protection element is secured to the electrical component and is positioned adjacent to the EMI reduction element so that the middle portion is closer to the distal end of the electrical component than the distal side of the EMI reduction element. The protection element protects the reduction element from being sheared and/or torn by walls of an enclosure that the electrical component can be inserted into.

Abstract: An interrupt and status reporting method and structure for a timeslot bus communications protocol. In one embodiment, a peripheral bus is a timeslot bus configured to transmit information across the bus in frames. Each frame may include at least one timeslot dedicated to reporting interrupt and status information to a host computer system. An interrupt request bit may be transmitted by a peripheral to a peripheral bus host controller, and may signal a request for an interrupt by a peripheral device. The requesting peripheral device may also transmit a cause code, which may include general information about the cause of the interrupt request, and a parameter field, which may include specific information about the cause of the interrupt request. Additionally, a peripheral device may be configured to use the interrupt and status reporting structure to request data to be transmitted to it from a host controller.

Abstract: An improved system for database query processing by means of “query decomposition” intercepts database queries prior to processing by a database management system (“DBMS”). The system decomposes at least selected queries to generate multiple subqueries for application, in parallel, to the DBMS, in lieu of the intercepted query. Responses by the DBMS to the subqueries are assembled by the system to generate a final response. The system also provides improved methods and apparatus for storage and retrieval of records from a database utilizing the DBMS's cluster storage and index retrieval facilitates, in combination with a smaller-than-usual hash bucket size.

Abstract: Disclosed herein is a method of determining an active region for a routing area having a plurality of component tiles positioned thereon. A set of stop points, each generally aligned with a lower edge of the routing area, an upper or lower edge of one of the component tiles, or an upper edge of the routing area, are determined. A component tile density interval is determined for a sweep line which corresponds to the lowermost stop point. The component tile density interval is then redetermined, in ascending order, for sweep lines generally aligned with each of the other stop points in the set. Along each sweep line, the component density is incremented by one for the horizontal span of a component tile for which the lower edge thereof extends therealong and decremented by one for the horizontal span of a component tile for which the upper edge thereof extends therealong.

Abstract: A computer system comprises a host processor, a temperature sensor for sensing temperature in an enclosure of the system and one or more fans for cooling the enclosure. A service processor is provided for providing system management functions within the computer system. These include generating fan speed signals in response to temperature values detected by the temperature sensor, and generating a control signal. The system includes a fan controller for providing power for driving the fan or at least one of the fans in response to the fan speed signals generated by the service processor only when the fan controller also receives the control signal from the service processor. In the absence of the control signal from the service processor, the fan controller will increase the fan speed to a predetermined fan speed, for example maximum, in order to ensure that no damage occurs in the event of a service processor malfunction.

Abstract: A system and method for automatically partitioning application components of a web application between a web server and an application server. Both the web server computer and the application server computer may implement an application component container. A method for programmatically analyzing the application components to determining an appropriate partitioning of the application components between the web server and application server computers may be employed. A deployment computer system may be connected to the web server and application server computers through a network. After the application components have been analyzed to determine an appropriate partitioning of the application components between the web server and the application server, the deployment computer system may then automatically deploy the application components on the respective computer systems according to this determined partitioning.

Abstract: A computer system I/O node. An input/output node for a computer system includes a first receiver unit configured to receive a first command on a first communication path and a first transmitter unit coupled to transmit a first corresponding command that corresponds to the first command on a second communication path. The input/output node also includes a second receiver unit configured to receive a second command on a third communication path and a second transmitter unit coupled to transmit a second corresponding command that corresponds to the second command on a fourth communication path. Further, the input/output node includes a bridge unit coupled to receive selected commands from the first receiver and the second receiver and configured to transmit commands corresponding to the selected commands upon a peripheral bus.

Abstract: A microprocessor configured to store victimized instruction and data bytes is disclosed. In one embodiment, the microprocessor includes a predecode unit, and instruction cache, a data cache, and a level two cache. The predecode unit receives instruction bytes and generates corresponding predecode information that is stored in the instruction cache with the instruction bytes. The data cache receives and stores data bytes. The level two cache is configured to receive and store victimized instruction bytes from the instruction cache along with parity information and predecode information, and victimized data bytes from the data cache along with error correction code bits. Indicator bits may be stored on a cache line basis to indicate the type of data is stored therein.

Abstract: A program execution data trace is created by instrumenting a program to record value sets during execution and an instruction trace. By simulating instructions either backward or forward from a first instruction associated with a recorded value set to a second instruction according to the instruction trace, a value set is determined for the second instruction. Backward and forward simulation can be combined to complement each other. For backward simulation, a table of simulation instructions is preferably maintained, which associates program instructions encountered in the instruction trace with simulation instructions which reverse the operation of the of the associated program instructions. Preferably, one or more probes is inserted into the program to save values of particular variables whose value may be difficult to determine. Preferably, the instruction trace is displayed alongside and correlated with the data trace.

Abstract: A method for constructing a capacitor having an increased equivalent series resistance (ESR) is disclosed. In one embodiment, a capacitor includes a plurality of capacitor plates comprised of a conductive material and first and second capacitor terminals. At least one of the capacitor plates is coupled to the first terminal and at least one of the capacitor plates is coupled to the second terminal. At least one of the plurality of capacitor plates includes a pattern, wherein the pattern is void of conductive material. The void in the conductive material formed by the pattern may cause a path of current flow through the capacitor plate to be substantially altered in comparison to a capacitor plate that is continuous. By using capacitor plates having voids of conductive material that cause the current path to be altered in comparison to continuous capacitor plates, a capacitor can be constructed having a higher ESR.

Abstract: An ejector mechanism (14) for a circuit board (21) and back plane (61), the ejector mechanism being operable to provide resiliently biased engagement between a first part (10) of an electrical connector (8) and a mutually engaging second part (12) of the electrical connector (8), the first and second parts of the electrical connector providing electrical connection for a plurality of electrical channels between the circuit board on which the first part is mounted and the back plane on which the second part is mounted. The ejector mechanism comprises an engaging projection (42) and a lever arm (40) pivotally mounted on one of the circuit board and the back plane and configured to engage the engaging projection (42) forming part of the other of the circuit board and the back plane.

Abstract: A graphics subsystem including a RAMDAC for connection to a graphics bus implemented on an integrated circuit chip separate from a graphics processor. In one embodiment, the graphics processor is configured to render digital image information in response to graphics commands and to store the digital image information in a memory. The RAMDAC IC includes a conversion unit, which includes a color mapping unit and a digital-to-analog converter and is configured to convert a representation of the digital image information into one or more analog signals for driving a video display. The graphics subsystem further includes a Direct Memory Access (DMA) controller implemented on the second integrated circuit chip. The DMA controller is configured to generate read requests to retrieve the digital image information stored in the memory to thereby cause the digital image information to be provided to the conversion unit.

Abstract: A method of manufacturing a metal layer structure and a corresponding integrated circuit chip are provided, wherein the integrated circuit chip comprises metal layers and via holes. The via holes electrically connect a metal line of one metal layer with a metal line of another metal layer. The metal lines and via holes form a signal path that electrically connects a first tap with a second tap. The metal lines in each metal layer are arranged in a first predefined configuration. There is for each metal layer a second predefined configuration that arranges the metal lines in the metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path that electrically connects the first tap with a third tap. This technique is particularly useful for storing revision identification data.

Abstract: A technique for measuring peak voltages is provided that may be used in RF transceivers or receivers of wireless local area network systems. In an apparatus for measuring a peak value of an analog voltage, an analog to digital converter is connected to receive an input voltage. A voltage level detection unit detects a voltage level of a received input voltage, and a digital memory receives and stores the detected voltage level. The digital memory updates the stored voltage level only if the currently detected voltage level is higher, or lower, than the stored level. A digital code is output that corresponds to the stored voltage level. The provided technique may allow for a more simple and less complex implementation.

Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The PCB may include a signal layer for conveying signals to and from the integrated circuit, but does not include any means for providing core power to the integrated circuit. Thus, all core power provided to the integrated circuit may be supplied by the power laminate.

Abstract: Provided is a method, system, and program for enabling a client to access a service, wherein the client is capable of communicating with a server. The client accesses an object from the server that includes code to enable the client to access the service. The accessed object includes a request rate indicating a rate at which the client transmits requests for the service. The client generates requests for the service using code included in the object accessed from the server. The client then transmits the generated requests for the service at the request rate included in the object.