Abstract: A memory controller controls access to one or more memory units. The memory controller includes access control logic operable to receive a memory access request that references at least one memory address. It further includes a fake response record operable to record a fake response indication for an address for which a response is to be faked. The access control logic is operable on receipt of a memory access request to access the fake response record and to fake a response where a fake response indication for an address indicates that a response is to be faked. By providing such a faked response, an embodiment of the invention is able avoid multiple exceptions for the same memory location in a CPU. Also, by providing such a faked response, multiple bus errors for a memory location can also be avoided where a bus supports Direct Memory Access (DMA). The memory controller can be implemented in an integrated circuit.

Abstract: Resource access control is provided in a manner that avoids unnecessary resource accesses where a resource is already known to be faulty. The resource can be a memory location, a peripheral or any other addressable system component. A resource access mechanism in a processor controls access to resources. The resource access mechanism includes an address control mechanism having a plurality of address control entries, each address control entry providing fake response identification indicating whether or not a response for the corresponding address is to be faked. The resource access mechanism also includes a fake response generator for selectively generating a faked response for an address in response to the fake response identification of the corresponding address control entry indicating that a response is to be faked.

Abstract: Resource access control is provided in a manner that avoids unnecessary resource accesses where a resource is already known to be faulty. A resource access controller controls access to resources addressed by at least one central processing unit. The resource access controller includes an address translation mechanism providing fake response identification as to whether or not a response is to be faked. The resource access controller also includes a fake response generator for selectively generating a faked response where the fake response identification of the corresponding translation entry indicates that a response is to be faked. The resource access controller is able to associate fake response indications with a resource and to generate a fake response when an attempt is made to access a resource labeled such that a faked response should be returned.

Abstract: The present invention provides a method and apparatus for inter-domain data transfer. The method includes mapping a memory region of a source device into a central device and mapping a memory region of a target device into the central device. The method further includes transferring data from the mapped memory region of the source device to the mapped memory region of the target device.

Abstract: An embedded system comprising a CPU and non-volatile memory is adapted to extend the endurance of the non-volatile memory through the use of an encoding of information stored in the non-volatile memory. One or more data bits are encoded into a larger number of non-volatile memory bit patterns such that changes to the data bits are distributed across fewer changes per non-volatile memory bit. Non-volatile memory endurance is extended since more changes to the data values are possible than can be supported by underlying changes to individual non-volatile memory bits. Word pre-erase, if present, can be accommodated as well as memory bit failures.

Abstract: A system unit includes a media drive bay. The media drive bay includes a metal drive bay housing configured to receive a media drive. A connector is provided to interface with a connector on a received media drive. A resilient tongue integral with the media drive bay housing is operable to urge onto a received media drive to hold the media drive in place and to ground a casing of the media drive. A detent is provided for latching a latching member attached to the media drive casing. The media drive can be a commercially available media drive for non-removable use, the media drive being modified by the provision of the latching member to provide for removability.

Abstract: An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus and the second transceiver unit may receive and transmit packet transactions on a second link. The packet tunnel may convey selected packet transactions between the first and the second transceiver unit. The graphics engine may receive graphics packet transactions from the first transceiver unit and may render digital image information in response to receiving the graphics transactions. The graphics interface may receive additional graphics packet transactions from the first transceiver unit and may translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

Abstract: A methodology for determining the placement of decoupling capacitors in a power distribution system and system therefor is disclosed. In one embodiment, a method for determining the placement of decoupling capacitors in a power distribution system includes determining target impedance, creating a power distribution system model, performing an LC (inductive-capacitive) resonance analysis, and performing a cavity resonance analysis. During the performance of the LC resonance analysis, capacitors may be selected in order to suppress impedance peaks resulting from LC resonances. Following the LC resonance analysis, the method may place the capacitors in the power distribution system at evenly spaced intervals. During the performance of the cavity resonance analysis, the capacitors may be repositioned in the power distribution system so as to suppress cavity resonances.

Abstract: A cluster implements a virtual disk system that provides each node of the cluster access to each storage device of the cluster. The virtual disk system provides high availability such that a storage device may be accessed and data access requests are reliably completed even in the presence of a failure. To ensure consistent mapping and file permission data among the nodes, data are stored in a highly available cluster database. Because the cluster database provides consistent data to the nodes even in the presence of a failure, each node will have consistent mapping and file permission data. A cluster transport interface is provided that establishes links between the nodes and manages the links. Messages received by the cluster transports interface are conveyed to the destination node via one or more links. The configuration of a cluster may be modified during operation.

Abstract: A cover for a access opening in a face of a housing of an electronic circuit module for a rack-mounted circuit is described, wherein the cover is pivotable to overlie a part of the face of the housing adjacent to an access opening closed by the cover. A hinge assembly for such a cover is described.

Abstract: A computer system includes a read ahead engine that receives a sequence of read requests and performs read ahead operations in accordance with various patterns detected within the sequence of read requests. The prefetch engine may implement the method of storing a first run value indicative of the run size of a first plurality of sequential read requests, and storing a first skip value indicative of a non-sequential skip associated with a subsequent read request. The method may further include determining whether a second run value indicative of the sequential run size of a second plurality of read requests equals the first run value, and whether a second skip value indicative of another non-sequential skip associated with an additional read request equals the first skip value. If the first run value equals the second run value, and the first skip value equals the second skip value, a stride pattern is indicated, and one or more read ahead operations according to the detected stride pattern may be initiated.

Abstract: A computer system comprises a plurality of processes, each having an associated memory region, and a shared memory region shared by the processes. One of the processes is configured to control allocation of space for an array in the shared memory region, generate a descriptor therefor pointing to the allocate space and transmit the descriptor to the other processes. Therafter, all of the processes are configured to identify regions of the array for which they are to process data therein, and to perform predetermined processing operations in connection therewith.

Abstract: A dirty memory that includes dirty indicators settable to indicate dirtied pages of memory is provided with control logic operable automatically to interrogate the dirty memory to identify dirty indicators that are set. Implementing the control of the dirty RAM in hardware or firmware enables interrogation of the dirty RAM to identify set dirty indicators in a rapid and reliable manner. The control logic can advantageously be operable to interrogate the dirty memory word-by-word to determine words including a set bit. A comparator can be provided for comparing bits of a word to a predetermined value to determine where a dirty indicator is set. The comparison could be performed serially for bits within a word, but it is advantageously done in parallel for the bits of the word. For example, by using associative memory, the interrogation of the dirty memory could be effected associatively in parallel to determine words including a word with a set bit.

Abstract: An application transaction (AT) server collects multiple user specified application operations for processing as a single application transaction and records essential information about each transaction being performed in a database. Such recordation enables the values of objects targeted by the particular application transaction prior to completion of a transaction to be restored in case of failed operation of the application transaction.

Abstract: The disclosed system is directed towards a tray bracket. The tray bracket comprises a tray bracket inlet, the tray bracket inlet has tray bracket inlet coupling elements. A tray bracket outlet is coupled to the tray bracket inlet and the tray bracket outlet has a body. The tray bracket includes a plurality of tray bracket outlet passages contiguous with the body. The plurality of tray bracket outlet passages are aligned with fan passages of at least one fan unit. The tray bracket outlet passages and the fan passages provide low impedance to air flow and low noise. The tray bracket includes attaching mechanisms contiguous with the body. The attaching mechanisms are manually demountably coupled to the tray bracket inlet coupling elements.

Abstract: A dirty memory for a computer system is configured hierarchically. This provides for more rapid identification of pages of memory that have been dirtied and require attention. For example for the reintegration of an equivalent memory state to the memories of respective processing sets in a fault tolerant computer following a lockstep error. The dirty memory includes at least two levels. A lower level includes groups of dirty indicators, each dirty indicator being settable to a given state indicative that a page of memory associated therewith has been dirtied. At least one higher level includes dirty group indicators settable to a predetermined state indicative that a group of the lower level associated therewith has at least one dirty indicator in a state indicative that a page of memory associated therewith has been dirtied. There can be more that two layers. Logic controls the operation of the hierarchical dirty memory.

Abstract: An arbitration method and mechanism assigning priority to one of a combination of requesters. A priority vector for the combination of requesters has a sequential list of requester identifiers. Upon receiving requests from the combination of requesters, the corresponding priority vector is referred to and the next requester identifier on this list is selected. Priority is awarded to the requester corresponding to that requester identifier. A priority vector is preferably provided for each possible combination of multiple requesters. The list of requester identifiers in each priority vector may be advantageously programmable. Preferably, all requester identifiers for a single requester are not provided in a contiguous clump within a given priority vector.

Abstract: A modular computer system mechanical interconnection includes a primary chassis having a first opening and a secondary chassis attached to the primary chassis and having a second opening, wherein the first opening and the second opening are generally aligned. The apparatus further includes a backplate covering the aligned first opening and second opening.

Abstract: An efficient clock start and stop apparatus for clock forwarded system I/O. The apparatus may include a buffer coupled to receive incoming data from a data source. The buffer is clocked by a first clock signal that is provided by the data source. The buffer is configured to store the incoming data in a plurality of sequential lines in response to the first clock signal. The buffer may be further configured to store a plurality of bits in a plurality of occupied-bit registers. Each one of the plurality of occupied-bit registers indicates that data is present in a corresponding sequential line in the buffer. The apparatus may further include a clock gate circuit coupled to the buffer and configured to provide a second clock signal. The clock gate circuit may be further configured to start the second clock signal when valid data is present in the buffer and to stop the second clock signal when no data is present in the buffer.

Abstract: An asymmetric multi-converter power supply including a first converter and a second converter coupled to provide power to an output node. A control circuit is coupled to the second converter and is configured to selectively enable the second converter depending upon a voltage at the output node. The control circuit may be configured to enable the second converter only in response to determining that the voltage at the output node is not within a predetermined range. Alternatively, the first converter is configured to provide power through a first series inductor and the second converter is configured to provide power to the output node through a second series inductor. The second series inductor having a smaller inductance than the first series inductor. Additionally, the second converter may be characterized by a transient response time that is faster than a transient response time of the first converter.