Abstract: The present invention relates to a method and related structure for reducing ground bounce during write operations from a microprocessor. More specifically, the address and data signal lines of the microprocessor are divided into three transmission groups. The first transmission group transitions its data onto the bus lines with no delay. The second transmission group transitions its signal lines onto the bus with a half clock period delay of the core frequency clock. Finally, the third transmission group transitions its signal lines onto the bus with a full clock period delay of the core frequency clock. In this way, parallel writes by the microprocessor have their current sinking associated with that write distributed over an entire clock period of the core frequency clock such that ground bounce associated with that current sinking is reduced.

Abstract: A victim record table records victim blocks which have been returned from a cache to memory and which are not currently cached in any other caches. If a command affecting a block recorded in the victim record table is received, one or more probes corresponding to the command may be inhibited even if probes would ordinarily be transmitted for the command. System bandwidth which would be consumed by the probes may be conserved. Furthermore, since probes are inhibited, the latency of the command may be reduced since the command may be completed without waiting for any probe responses. Since probes are selectively inhibited if an affected block is recorded in the victim record table, the size of the victim record table may be flexible. If a particular block is not represented in the victim record table, probes are performed when the particular block is accessed (even if the particular block could have been represented in the victim record table but is not because of a limited number of records).

Abstract: A peripheral interface circuit for handling graphics responses in an I/O node of a computer system. A peripheral interface circuit includes a buffer circuit coupled to receive packet commands. The buffer circuit includes a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected packet commands that belong to the respective virtual channel. The peripheral interface circuit may determine whether a given one of the received packet commands is a graphics response belonging to a particular respective virtual channel. In response to determining that the given packet command is a graphics response belonging to the particular respective virtual channel, the buffer circuit may cause the given packet command to bypass the plurality of buffers.

Abstract: A system for communicating between a first network and a second network, wherein the first network may alternately communicate through one of a plurality of communication devices, each having a different IP address. In one embodiment, the first network is contained in a vehicle. The first network initiates communications through one of the communication devices and communicates the IP address of this currently-used device to a proxy server. If communications are lost, the first network attempts to establish communications through another of the communication devices. In a first mode, the first network communicates with the second network directly, using the IP address of the currently-used communication device for return communications. In a second mode, the first network communicates with the second network directly, but return communications are routed through the proxy server, which forwards them to the first network.

Abstract: A method of joining a plurality of sheets by means of a blind rivet, comprises: (i) forming holes in the sheets and placing the sheets together so that the holes are in register and form a single hole therethrough; (ii) inserting a blind rivet into the hole formed in the sheets from a working side thereof, the blind rivet comprising a sleeve (1) positioned about a mandrel that has a head (4); and (iii) setting the rivet. The hole (24) is radially enlarged at the outwardly facing surface of at least the sheet on the blind side, and the sleeve of the rivet is deformed during setting to form a rivet joint in which no part of the rivet is proud of the outwardly facing surface (28) of the sheet at least on the blind side of the sheets. The method enables rivet joints to be formed in sheets, for example used in enclosures that house modules, where there is no space available for the set rivets to protrude.

Abstract: There is described a support rail and a support element for engaging an edge of an expansion card mounted in a circuit housing, wherein the support element is fixable in a selected position along the length of the support rail by engagement of a detent on the support element and a facing abutment surface on the rail.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Abstract: A fan control module is provided for a system unit. The fan control module includes power outputs for supplying power to a plurality of fan. It also includes a temperature sensor for giving a temperature signal. It further includes a control unit connected to receive the temperature signal and including preprogrammed control information for determining power signals to be supplied to each of the fan units for controlling the speed thereof. The fan control module can control the fan units in a coordinated manner enabling reliable and effective cooling of the system unit under widely varying parameters. It can mean that existing system components can be employed in harsher temperature environments that they were originally designed for, without needed a complete redesign thereof. The fan control module can be provided with electrical noise isolation circuitry to isolate other components from electrical noise generated by the fan units.

Abstract: A system and method for providing a common power detect and presence detect signal. In one embodiment, a memory module includes a voltage regulator and a power detector circuit. The voltage regulator may be configured to provide a stable operating voltage to the various circuits of the memory module. The power detector circuit may be configured to detect the presence of the operating voltage from the output of the voltage regulator. The power detector circuit may assert an output signal in response to a detection of a voltage from the voltage regulator. The output signal asserted by the power detector circuit may then be driven through a single pin of a connector mounted to the memory module to a storage unit of the host computer system. The storage unit may be configured to store the state of the output signal.

Abstract: A system and method for synchronizing the skip pattern to two clock domains and initializing the clock skipping buffer which enables data transfers between the two clock domains. In one embodiment, a circuit comprises a pair of alignment detection units, a synchronous reset unit, a skip pattern generator, a counter reset unit and a data transfer buffer. Each of the alignment units is configured to detect the alignment of the clock signal in one of the clock domains with a reference clock signal and generate a signal indicative of the alignment. This signal is conveyed to the synchronous reset unit and the counter reset unit. The alignment signal generated by one alignment unit is also conveyed to the skip pattern generator. The synchronous reset unit accepts the alignment signals from the alignment units and generates concurrent reset signals (i.e., one for each of the two clock domains) to initialize the counter reset unit.

Abstract: Disclosed herein are a method and apparatus to provide a deterministic power-on voltage in a system having a processor-controlled voltage level. In one embodiment, the system includes a DC/DC converter, a processor, and a selection circuit. The DC/DC converter receives a voltage setting signal or signals from the selection circuit and provides an adjustable power output signal having a voltage indicated by the voltage setting signal. The processor is powered by the adjustable power output signal. When powered, the processor provides a programmable voltage setting signal or signals. The selection circuit receives the programmable voltage setting signal or signals, a hardwired voltage setting signal, and a selection signal or signals, and when the selection signal is in a predetermined condition, the selection circuit provides the programmable voltage setting signal or signals from the processor to the DC/DC converter.

Abstract: A method for determining changed code in a second program binary relative to a first or baseline program binary, where the second program is a different version of the first program, includes translating, responsive to symbol tables and/or control flow representations, machine addresses of both program binaries to symbols. The first and second program binaries are disassembled using the translated symbols. Differences between the two resulting disassemblies are determined, and a list of the differences is created. Differences between the program binaries can be determined by textually comparing the disassemblies, or alternatively, by determining the differences between the control flow representations of the programs. The list of differences can be presented to a user, or alternatively, can be passed to another process for further processing, such as test coverage analysis, code change analysis, or failure analysis, among other analyses.

Abstract: A PLL frequency synthesizer able to automatically set an appropriate operating mode of the voltage controlled oscillator is provided. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The appropriate operating mode is selected based on an error signal detected by a phase/frequency detector of the PLL frequency synthesizer. A window comparator is used for switching to adjacent operating modes if the error signal exceeds or falls below predefined upper and lower error voltage limits.

Abstract: A data storage subsystem including an array of storage devices and a storage controller is disclosed. In one embodiment, the array of storage devices stores information in multiple stripes. Each stripe may include a plurality of data blocks and redundancy information in the form of plurality of redundancy blocks. The redundancy information may be generated using an nth order generator polynomial such as a Reed Solomon code. The storage controller may be configured to perform modified read/write stripe updates by: (a) reading original data from a subset of data blocks in a target stripe; (b) reading the original redundancy information for that stripe; (c) comparing the original data with the new data to determine a data difference; (d) calculating a redundancy difference from the data difference; (e) applying the redundancy difference to the original redundancy information to obtain updated redundancy information, (f) writing the new data and updated redundancy information to the target stripe.

Abstract: A method for controlling thermal cycles in a computer system is provided. The method is comprised of receiving a request to transition the computer system from a first operating mode to a second operating mode, where less power is consumed in the second operating mode. A historical rate at which the computer system has transitioned between the first and second operating modes is determined, and the requested transition is permitted in response to the historical rate being less than a first preselected setpoint, but denied in response to the historical rate being greater than the first preselected setpoint.

Abstract: A computer method for issuing an early warning includes determining, using change and test coverage and control flow and data flow analyses of a program, locations in the program at which to insert early warning (EW) code to monitor for an event. The program is instrumented with EW code which monitors for the event, by inserting EW code at the determined locations. Upon detecting the event, EW code performs an early action warning, or issues an early action. Early warnings are issued when an EW-instrumented block is reached. Issuance of an early warning action can be conditional upon execution of the program in a particular environment, such as a production environment. Issuance of an EW can also be conditional upon executing an untested block of code that was recently modified.

Abstract: An elongate gasket that can be placed on an electrical assembly in order to reduce electromagnetic interference, comprises (i) an elongate deformable strip (1) of electrically conductive material that has been folded along its length to form an arcuate cross-sectional profile; and (ii) an attachment arrangement (10, 12) to secure the gasket onto the component; At least one of the strip and the attachment arrangement is folded at an end region (30) thereof over the end of the other of the strip and the attachment arrangement in order to provide a smoothly varying longitudinal profile at the end of the gasket. This form of gasket allows components such as modules, to be inserted into recesses in an assembly by sliding along the gasket without damage to the gasket or causing it to be shifted.

Abstract: A system and method for synchronizing mirrored and striped disk writes. A data storage system may include a client computer system coupled to a first data storage device and a second data storage device and configured to transmit a first data write request. The first storage device may be configured to transmit a sequence number to the client computer system in response to receiving the first data write request. The client computer system may be further configured to transmit a second data write request including the sequence number to the second storage device. The second data storage device may include a counter and is configured to compare a current counter value to the sequence number. If the counter value is equal to the sequence number, the second storage device stores the data bytes corresponding to the second data write request and increments its counter.

Abstract: A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into the coherent communication fabric and directed to a first target. Issuance of the second request into the coherent communication fabric is stalled until the first target receives and orders the first request and transmits a response acknowledging the same.

Abstract: A system and method for backing up data from a plurality of client computer systems. A server computer executes a plurality of processes each configured to receives back-up data from a respective one of the client computers. Each of the processes stores the back-up data into a buffer within a shared memory area. The server computer associates an identification tag with each set of back-up data which identifies from which particular client computer the data was received. The server computer then stores the back-up data and the identification tags within a storage unit. Data from a particular client is de-multiplexed from the storage unit by scanning all of the identification tags in the storage unit and sending any data which is associated with a received identification tag to the particular client.