Abstract: An apparatus and method for testing an integrated circuit (12) generally comprises an input pad (14) and output pad (15) having photo-sensitive sensors (20, 46) formed thereon for eliminating the need to come into direct contact with a probe card for testing the integrity of an integrated circuit.

Abstract: An apparatus (10) and method is provided for bonding wire (12) to the bond sites (28) of integrated circuits (14). In preferred embodiments a bond end (30) on gold wire (12) is bonded to aluminum bond pad (28). Apparatus (10) includes a high frequency ultrasonic energy source (20) designed to provide ultrasonic energy at frequencies from about 100 kHz to about 125 kHz. The ultrasonic energy is imparted to the bonding interface (32) via transducer (18) and capillary (16). The transducer (18) is modified in length and tool clamp point (40) is sited on transducer (18) so that the high frequency ultrasonic energy is at the antinodal point in its application to interface (32) and thus is optimized. In preferred embodiments of the process, the ultrasonic energy is applied at about 114 kHz. In this fashion, the bond formed between bond end (30) and bond pad (28) is optimized in terms of shear strength, bonding time and processing temperatures.

Abstract: A linear, direct-drive microelectronic bonding apparatus (10) provides a bondhead mounting plate (20), a stationary magnetic circuit (21), a moving coil (22), a primary wire clamp housing (23), a transducer mount (24), and a high frequency ultrasonic transducer (25) (above 100 kHz), and a capillary (26). Bondhead assembly (16) is configured to present a collective axial wire path bore (27) along which wire (12) is fed to bond site (28) for forming microelectronic bond interconnections at bond site (28). In accordance with the invention, collective wire path bore (27) provides a protected method of feeding wire (12) to bonding site (28), while magnetic circuit (21) and moving coil (22) provide actuation in a substantially linear downward direction towards the bonding site. In contradistinction, prior art bonding strokes, rather than being substantially linear, are arc-like due to the capillary and transducer being perpendicular to one another.

Abstract: A method of testing for cell to bitline leakage using an improved algorithm is disclosed. A selected portion of the bitlines, both true and complement, are changed. In this manner, the entire memory can be tested without regard to memory size. The prior algorithm used to perform this same function on a megabit dram would take about 570 seconds. The new procedure performs the same function in a more efficient manner, resulting in a test time of approximately 2.8 seconds which is over 200 times faster.

Abstract: An LCD drive circuit includes a voltage divider circuitry which generates a plurality of voltages (V.sub.1 -V.sub.5) in response to a reference voltage. A substantially constant reference voltage is generated by a band-gap reference circuit (22). A digital-to-analog converter (32) allows the voltages to be adjusted responsive to digital control signals.

Abstract: A test circuit (10) is connected to a package pin of an integrated circuit via the first node (16). By setting the voltage on the package pin to a sufficient voltage, the test circuit becomes operable to measure DC characteristics of devices in the test circuit. The DC characteristics of the test circuit devices, such as resistors (26 and 34), diodes (44) and transistors (30 and 32) are used to estimate the AC characteristics of the actual integrated circuit. The AC characteristic estimations may be used to screen parts into various speed classes.

Abstract: A method and film/interconnect lead combination for attaching a plurality of sets of interconnect leads on a strip of film using an adhesive which loses bonding strength upon being exposed to energy such as heat or ultra violet light. The film holds the interconnect leads firmly in their proper position for bonding to an integrated circuit chip and to a leadframe or substrate such as a printed wiring board or a ceramic substrate for hybrid circuits. Either during or after bonding the interconnect leads to the leadframe or substrate, energy is applied to the adhesive holding the interconnect leads to the film and the film is detached from the interconnect leads in a manner which will not damage the leads due to the reduced adhesive strength. Thus, the leadframe package will not enclose the film.

Abstract: A method and apparatus for polishing semiconductor wafers in which a force applied to the wafer is uniformly distributed across a surface of the wafer during polishing using a hydrostatic or compliant material situated between the wafer and a piston. In a preferred embodiment, the hydrostatic or compliant material is an elastic solid or fluid filled bag. One or more teflon disks or teflon coated surfaces may be included between the hydrostatic or compliant material and a second compliant layer to form a bearing to allow the wafer to rotate about its central axis during polishing.

Abstract: A first polysilicon layer (18) is initially deposited onto a layer of field oxide (16). A dielectric (26) is formed on a portion of the first polysilicon layer (18). A second polysilicon layer (28) is deposited over the dielectric (26) and the first polysilicon layer (18). After the selective deposition of a mask (30) on to the second polysilicon layer (28), the polysilicon layers (18, 28) are anistropically etched to form a polysilicon to polysilicon capacitor (34) and a contact (36) of the capacitor (34). The dielectric (26) functions as an insulator for the capacitor (34) and as a barrier during anisotropic etching for protecting the underlying polysilicon layer (18).

Abstract: A programmable memory includes a voltage regulator (32) which is disposed between the supply voltage and the matrix supply line (10) for programmable memory cells. Each of the memory cells is comprised of a transistor (12) and a series of fusible link (16). By maintaining a constant voltage on the matrix supply line (10), transients on the supply pin of a memory chip cannot cause spurious changes in the logic state of the memory cell resulting from parasitic capacitance (28).

Abstract: A digital crossbar switch designed to facilitate easy and flexible interconnection of up to 8 data ports. The device includes 8 bidirectional ports, each 8 bit wide. Interconnection of the ports is controlled by 32 stored control memory locations associated with each port. The controlling memory locations can be changed dynamically without interfering with data flow. Additional program flexibility can be achieved by providing each port with a 16 word first-in first-out data buffer. The capability to bit reverse the data on any of the ports is also provided to simplify the interconnection of busses from different architectures. The device is fully expandable to wider busses, has extensive test capability and a master reset is provided for system initialization.

Abstract: An apparatus (10) and method is provided for bonding wire (12) to the bond sites (28) of integrated circuits. In preferred embodiments gold wire (12) is bonded to aluminum bond pad (28). Apparatus (10) includes a high frequency ultrasonic energy source (20) designed to provide ultrasonic energy at frequencies above about 100 kHz causing the interface temperature required for adequate bonding to be greatly reduced. Heating element (19) applies thermal energy to interface (32) via capillary (16) and transducer (18). Therefore, according to the invention, less thermal energy is required from heater block (22) which is heating interface (32) via IC (14) and leadframe (15). In this fashion, leadframe (15) is maintained at a lesser temperature than in the prior art. Since leadframe (15) is at a lesser temperature, it can be plated with a material having a lower melting point (e.g. tin or solder). In preferred embodiments, leadframe (15) is substantially plated with tin (melting point 185.degree. C.

Abstract: An edge detector includes a pair of integrated light sensors, a pair of log amplifiers and a comparator amplifier, having a hysteresis voltage applied thereto.

Abstract: An integrated circuit (42) is formed in a semiconductor layer (50) having a defined area. Functional circuitry (12) is formed in semiconductor layer (50) to occupy only a portion of the defined area of semiconductor layer (50), and thus defining an unoccupied area of semiconductor layer (50). A capacitor is formed in semiconductor layer in a substantial portion of the unoccupied area.

Abstract: An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.

Abstract: An integrated circuit is provided wherein bipolar, CMOS and DMOS devices are merged together on one chip with fabrication taking place from a CMOS point of view rather than from a bipolar point of view as in the prior art and p-type epitaxial silicon is used as opposed to n-type epitaxial silicon in the prior art. The integrated circuit uses a P+ substrate upon which a P-epitaxial layer is formed. N+ buried regions isolate the DMOS, PMOS and NPN bipolar devices from the P-epitaxial layer. Each of the devices is formed in a N-well with a first level of polysilicon gate layer providing both the gate and masking for the backgate diffusion of the DMOS device and a sidewall oxide later formed on the first level gate layer to control the diffusion of the source and drain regions of the DMOS device to control channel length. A second level of polysilicon layer provides the gate structures for the CMOS devices as well as one plate of a capacitor.

Abstract: A sample and hold circuit (24) is provided which includes an input terminal (36) for receiving a time varying input voltage. A first capacitor (14) maintains a first voltage corresponding to a sample of said time varying input voltage. A switch (12) having a control terminal (20) is operable to sample the input voltage by coupling input terminal (36) to first capacitor (14) in response to a sampling signal provided at control terminal (20). At least one second capacitor (58, 86) is provided for maintaining a preselected voltage. Circuitry (40, 42, 68, 106) is provided for selectively applying the sampling signal to control terminal (20) of switch (12) by impressing at least the preselected voltage maintained by second capacitor (58, 86) on control terminal (20).

Abstract: A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective source regions (30a, 30b), a shared drain region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) that controls the conductance of a respective subchannel region (74a, 74b) and may be programmed through Fowler-Nordheim electron tunneling through a respective tunnel oxide window (40a, 40b) from a respective source region (30a, 30b). A field plate conductor (40a) controls the conductance of respective subchannel regions (70a, 70b) within each channel region (38a, 38b). A word line or control gate conductor (62) is insulatively disposed adjacent respective third, remaining channel subregions (53a, 53b) and further is disposed insulatively adjacent the floating gates (46a, 46b) to program or erase them.

Abstract: AC stabilization and temperature compensation improves phase margin and permits high temperature (significantly above 125.degree. C.) operation for an exemplary low drop-out voltage regulator with a PNP output transistor. The low drop-out voltage regulator (FIG. 1) includes a PNP output transistor (Q.sub.OUT) together with a voltage reference circuit (12), a gain circuit (14), and a current limit circuit (16). To provide AC stabilization, a small internal capacitor (C.sub.INT) of about 10 pF is coupled between the input of the gain circuit and the base of the output PNP, using Miller multiplication to substantially increase the effective capacitance of the stabilization capacitor, and introducing a zero into the gain-phase plot for the voltage regulator, substantially cancelling the pole, with a concomitant increase in phase margin. To provide temperature compensation, a dual-collector temperature compensation PNP (Q.sub.

Abstract: Apparatus for enhancing capacitance matching in a multi-stage capacitor network of an A/D converter is provided. The stages are coupled to one another by a coupling capacitor having a top and bottom plate. The apparatus comprises a first shield overlying the capacitor network, where the shield is coupled to a known potential. A second shield is positioned over each of the coupling capacitors, where each second shield is separate from the first shield and coupled to the bottom plate of each respective coupling capacitor.