Abstract: An enclosed plating wheel system includes a fixed mounted shaft, feed and return spargers mounted on the shaft, and a plating wheel rotates around the fixed mounted spargers as a result of a lead frame strip being pulled around the plating wheel. A belt is also rotated around a portion of the plating wheel assembly over the lead frame strip to contain the plating solution within the plating wheel assembly.

Abstract: A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD.

Abstract: A set of event qualified test protocols for use in testing integrated circuits is disclosed. A boundary scan architecture for use in the integrated circuit (10) comprises input and output test registers (12,22) having functions controlled by an event qualifying module (EQM) (30). The EQM (30) receives a signal indicating a matching condition has been met. The EQM receives additional signals which indicate which testing protocol of the possible protocols is selected. The EQM (30) may control the input and output test registers (12,22) to perform a variety of tests on the incoming and outgoing data. During testing, the internal logic (20) may continue to operate at speed, thereby allowing the test circuitry to detect faults which would not otherwise be observable. A memory buffer (64) may be included to store a plurality of input data for test data. A set of standard protocols is disclosed which allows interoperability between EQMs on multiple IC's in a circuit.

Abstract: A non-invasive sensor system (50) for real-time in situ measurements of sheet resistance and thickness of conductive layers of a semiconductor wafer. The sensor (50) includes a microwave source (78) for generating a plurality of microwave signals. An emitter waveguide (52) receives the plurality of microwave signals from the microwave source (78) and emits the microwave signals in the direction of the semiconductor wafer (20) in fabrication chamber (18). The collector waveguide (84) detects the reflected microwave signals from the semiconductor wafer (20). A dual directional coupler (64) communicates with emitter waveguide (52) to direct the microwave signals to and from the emitter waveguide (52) and to generate a plurality of electrical signals that relate to semiconductor wafer (20), conductive layer (108), and deposition vapor physical characteristics. These physical characteristics include conductive layer thickness, resistivity, and substrate temperature.

Abstract: Field Effect Transistors are used to replace mechanical relays and to minimize the distance a Device Under Test (DUT) must drive a signal path to the receiver, to minimize insertion losses in critical paths to the DUT, and generally increase reliability in integrated test systems by eliminating the need for relays to test integrated circuits.

Abstract: A method and apparatus for sensing radiation 26 indicative of at least one process variable in a semiconductor process chamber 10 in which a reactant gas reacts to effect changes in a silicon wafer 12. The method comprises positioning a substantially transparent window 22 in a conduit 14 leading to the wafer 12 and then flowing the reactant gas in the conduit 14 past the window 22 and toward the wafer 12. The radiation 26 is then sensed through the window 22. In the preferred embodiment the window 22 is positioned with an optical path along the center axis of the conduit 14. Other systems and methods are also disclosed.

Abstract: A charge detection amplifier embodying the invention comprises a first amplification stage (Q10-Q15) coupled to an input terminal 70 and having an output node 72. Capacitive feedback is provided by a capacitor 82 coupled between an input node 71 and said output node 72. The operating bias point of said first amplification stage is set by a first balance circuit (Q16/Q17) coupled between said output node 72 and two internal nodes 74,76 of said first amplification stage, the magnitude of said coupling being controlled by a voltage applied to a first balance circuit input terminal 84. A first buffer stage 200 is provided to couple said output node 72 to a circuit output terminal 92 and to provide adequate current to drive an external load connected to said output terminal 92. A reset switch (Q24/Q25) is provided to short circuit said capacitor 82 in response to a signal applied to a reset terminal 104.

Abstract: A transistor is disclosed which comprises a gate conductor 34 insulated from a channel region 55 by a gate insulator layer 38. A spacer insulator block 46 is used to accurately space a drain region 52 a predetermined distance from the gate conductor 34. A dopant source body 48 is used to form the drain region 52 such that the formation of the drain region 52 is a self-aligned process. According to the teachings of the present invention, the drain region 52 can be accurately spaced from the gate conductor 34 to reduced field enhanced leakage current during the operation of the transistor.

Abstract: A translator circuit 82 and operation thereof is disclosed including a control signal generator 48 and an ECL output buffer circuit 84. Control signal generator 48 includes a CMOS inverter comprising transistors 52 and 54. The CMOS inverter is connected to a bipolar junction transistor (BJT) 70 which is further connected to as BJT 76. BJT 70 provides a voltage control signal, V.sub.CS, to ECL output buffer circuit 84. BJT 76 is connected as a transistor in a differential pair comprising transistors 76 and 86. An ECL output signal, V.sub.OUT, is generated in accordance with the operational state of transistors 76 and 86 and additional circuitry associated therewith.

Abstract: There is disclosed a light energy management system for use in conjunction with, in one embodiment, the exposure unit of a xerographic reproduction system. The light management system serves to funnel the unmodulated light for proper impact on a modulating device and to maintain the dark effect of the device when in the unmodulated mode. Light baffles are used for this purpose, some of which are formed as a series of angular steps designed to eliminate unwanted light along the longitudinal axis of the modulated light path. The angular step, in one embodiment, takes the shape of a semi-circular bee thorax. The modulated light path includes a light focus lens and a pair of mirrors for sending the modulated light pulses to the reproduction process surface.

Abstract: An etch process for etching copper layers that is useable in integrated circuit fabrication is disclosed which utilizes organic and amine radicals to react with copper, preferrable using photoenergizing and photodirecting assistance of high intensity ultraviolet light, to produce a product which is either volatile or easily removed in solution. The process is anisotropic.

Abstract: A lead frame locater is used to locate actual positions of lead frame leads in respect to the semiconductor chip to provide accurate wire bonding of the semiconductor chip to the lead frame leads.

Abstract: The disclosure relates to a method of forming in situ phosphorous doped polysilicon wherein a surface upon which phosphorous doped polysilicon is to be deposited is placed in a vacuum furnace and, after low pressure HCl cleaning of the surface and furnace, a predetermined ratio of silane and a gaseous phosphorous containing compound taken from the class consisting of phosphorous trichloride, tertiary butyl phosphine, isobutyl phosphine, trimethyl phosphate and tetramethyl phosphate are simultaneously passed through the furnace at predetermined pressure and temperature to provide a uniformly phosphorous doped layer of polysilicon on the surface.

Abstract: A first-in, first-out memory (10) can store a programmable number of data words at respective address locations within a memory (76). A read address generator (50, 58) generates a read pointer for pointing to a read address location in the memory (76). A depth address generator (42) points to a depth address location in the memory that is displaced from the read address location by a predetermined number of address locations. This depth address generator (42) is incremented to a next read depth address responsive to a read pulse (20) issued from a read/write controller (12). A write address generator (80) points to a write address location within memory (76). A comparator (52) compares the value stored in the write address generator (42) to the read depth address location stored in depth address generator (42) and is operable to generate a FULL memory status flag (24) responsive to their equality.

Abstract: A method of resetting deflectable pixels of a spatial light modulator is disclosed. A pulse train of voltage is applied to the device to cause it to mobe from its deflected position.

Abstract: An input circuit is provided which receives TTL voltage signals as input and transmits CMOS voltage signal levels. A separation transistor connected to a voltage divider network is included within the circuit to separate the two gates of a CMOS inverter from the TTL input such that one gate of the inverter is fully off when the other gate is on and fully on when the other gate is off. Thus internal ground voltage fluctuations during operation of the circuit are avoided.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: A TTL compatible CMOS high-speed lower-power supply-independent input buffer has a first current mirror which supplies current to a reference node of the input buffer when the signal at the input node of the buffer goes to a high state. An MOS transistor has its gate connected to the input node and switches hard on when the input node goes to a high level, pulling the reference node to a low level. A second current mirror is provided which injects current into the reference node for a predetermined period of time after the voltage level at the input of the buffer goes to a low level to pull the reference node to a high level. Both the first and second current mirror are switched on only during transition states of the input buffer, to minimize power dissipation when the input buffer is in its quiescent state.

Abstract: Apparatus for generating memory addresses for accessing and storing data in an FFT (Fast Fourier Transform) computation is provided. The FFT computation is typically performed by computing a plurality of FFT butterflies belonging to a plurality of ranks. The apparatus includes a butterfly counter for determining the current FFT butterfly being computed. The butterfly counter produces a plurality of butterfly carries. A rank counter for determining the rank of said current FFT butterfly being computed produces a rank number. Coupled to the rank and butterfly counters is incremental curcuitry, which generates an incremental number in response to the rank number and the butterfly carries. An adder circuitry coupled to the incremental circuitry adds the incremental number and a plurality of memory addresses to produce the FFT data memory addresses.

Abstract: An integrated circuit AC test and burn-in socket (10) for communicating test signals between test circuitry and an integrated circuit chip (11) comprises connection circuitry (32) associated to engage the chip (11) and communicate test signals between the chip (11) and the test circuitry. A compliant base (34) supports the circuitry (32) and assures positive engagement and electrical connection between the circuitry (32) and the chip (11). A socket assembly (20 and 21) holds the chip (11) in engagement with the connection circuitry (32).