Abstract: A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

Abstract: A layered dielectric structure is provided, which separates a first layer of metal interconnects from each other in semiconductor devices and also separates the first layer from a second, overlying layer of metal interconnects for making electrical contact to the first layer of metal interconnects. The layered dielectric structure comprises: (a) a layer of an organic spin-on-glass material filling gaps between metal interconnects in the first layer of metal interconnects; (b) a layer of an inorganic spin-on-glass material to provide planarization to support the second layer of metal interconnects; and (c) a layer of a chemically vapor deposited oxide separating the organic spin-on-glass layer and the inorganic spin-on-glass layer. The layered dielectric structure provides capacitances on the order of 3.36 to 3.46 in the vertical direction and is about 3.2 in the horizontal direction. This is a reduction of 10 to 15% over the prior art single dielectric layer, using existing commercially available materials.

Abstract: A system is provided for ensuring that a ethernet controller operates to optimize bus latency and central processing unit (CPU) utilization in a network environment when reviewing data packets. Through the efficient use of a plurality of buffer memories and a driver, the bus utilization in conjunction with the controller the system provides for the receipt and transfer of data packets from the ethernet controller during the latency period of the network. In so doing, the overall performance of the network is enhanced.

Abstract: The present invention is directed toward an combined decoder/adder circuit which provides faster access to a cache in a microprocessor than implementations which include an adder circuit which is followed by a decoder circuit. By decoding the upper order bits of a first operand and then rotating the upper order bits of the first operand by the upper order bits of a second operand, followed by an additional shift by one which is enabled by a carry generator the overall speed of the critical path is greatly increased. Accordingly, the time needed for generating an effective address (EA) and therefore accessing the cache is significantly decreased. The present invention has significant utility in microprocessors in which the word line decode is the critical path.

Abstract: A system and technique for storing data in a cache memory in record format and in track format. Space is allocated in cache memory for the storage of data in track format. Additional space is allocated for the storage of data in record format. Data is stored in both formats. The most current data is identified and addresses are generated for each record of data. Access to individual records of data is facilitated through a track information block in which pointers are stored for the most current records whether stored in track format or record format. The track information block facilitates a rapid storage and retrieval of data in either format. In a specific implementation, data is stored in either format in cache using a scatter index table. The scatter index table and associated track directory entries are stored in a shared control array. Each track directory entry points to a track slot header in a cache.

Abstract: A portable needle syringe destroyer apparatus that includes a housing with a handle, three lights and a switch on top and a metal plate on, the front at an oblique angle. The destroyer apparatus includes: a battery, battery charge monitor, battery charger and current regulator interior to the housing. The metal plate floats on a spring and moves when a needle is inserted into the opening on the plate. The current is applied through the switch to instantly heat the metal plate high enough and cause the immediate destruction of the needle, any pathogens on or in it and seal the syringe with a small metal ball at the needle hub. The result is irrevocably disposing of the needle and rendering their toxins harmless.

Abstract: A biasing arrangement for a quasi-complementary output stage having first and second transistors of a first type, where at least one of the transistors is driven by a third transistor of a second type. The inventive biasing arrangement comprises a first circuit for biasing the third transistor and a second circuit having a third circuit for providing an input signal to the first transistor and a fourth circuit for providing the input signal to the first circuit. In a particular implementation, the first circuit is connected between the input terminals of the first and the third transistors. The third circuit is a fourth transistor having a first terminal connected to a first source of supply, a second terminal connected to a source of the input signal and a third terminal connected to a second source of supply. The third terminal of the fourth transistor is connected to the second source of supply via a first resistor.

Abstract: A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

Abstract: An apparatus and method are provided which override the child-resistant features implemented on disposable lighters in the form of locking mechanisms that restrict the movement of the thumb lever. More specifically, in the practice of the invention, a band having a laterally extending projection or, alternatively, a slot, is slid onto the lighter body until the laterally extending projection or slot aligns with the locking mechanism of the lighter. The laterally extending projection or slot disengages the locking mechanism by moving it out of the path of the thumb lever so that the thumb lever may be depressed at will. Thus, the apparatus and method of the invention enable disposable lighters to be operated as if no child-resistant features are present.

Abstract: A fused glass block having an axial gradient index of refraction profile between two opposed parallel surfaces, with a change in refractive index from one of the surfaces to the other ranging from about 0.04 to 0.47, is provided. The fused glass block has a change in thermal expansion coefficient from one of the surfaces to the other of less than about 3.times.10.sup.-7 .degree. C..sup.-1, has essentially no strain or birefringence therein, and has a smoothly varying refractive index profile from one of the surfaces to the other. The fused glass block is prepared from at least two pre-selected compositions of a lead-silicate glass series that has been discovered to provide the requisite properties.

Abstract: A circuit is provided that allows for the substitution of a memory module with one type of addressing scheme with a second memory module which has a different type of addressing scheme. Through the use of a row address strobe (RAS) generator and address generator which receives multiple RAS signals, a new RAS signal is generated that is in accordance with the one type of addressing scheme and an address signal is provided which indicates which portion of the memory is to be accessed.

Abstract: A printed circuit board (PCB) capable of operating at first and second predetermined voltage levels including a plurality of metal layers, one of the metal layers being divided to provide two electrically isolated sections, the two electrically isolated sections being on substantially the same plane; one of the electrically isolated sections being associated with the first predetermined voltage level and the other of the electrically isolated sections being associated with the second predetermined voltage level. The PCB includes a first plurality of signal pins coupled to the one of the electrically isolated sections. The PCB also includes at least one capacitor coupled to a ground plane, the first plurality of signal pins and the one of the electrically isolated metal sections, wherein an alternating current path is provided. The PCB in a preferred embodiment is an expansion board utilized in a personal computer.

Abstract: An ABS adhesive for joining ABS articles, such as pipes, comprises: (a) about 10 to 35 wt% ABS resin; and (b) about 40 to 60 wt % dibasic esters and, optionally, at least one solvent selected from the group consisting of 0 to about 30 wt % methyl ethyl ketone and 0 to about 10 wt % acetone. The VOC level of the ABS adhesive composition of the invention is at or below the allowed maximum value of 350 g/l. The lap shear strength ranges from about 400 to 700 psi, which is deemed adequate for most non-pressure applications, such as drain, waste, and vent uses, and pool and spa applications.

Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

Abstract: A digital phase-locked data recovery circuit having improved noise immunity. The data recovery circuit includes a multi-phase clock for supplying clock signals having a predetermined relative phase relationship. A snap shot sampling network takes samples of an input data signal in response to the multi-phase clock signals. The samples are preferably collected during the duration of boundary sampling windows encompassing transitions in the input data signal. The present invention further includes a network for comparing the received data samples with a sample pattern. A phase encoder then generates error signals in response to the phase comparisons. A phase decoder adjusts the phase of the boundary window in response to the error signal.

Abstract: A method for detecting a half-full condition of a first-in, first-out memory array. The method of the invention includes the steps of a) moving a write pointer through the array to write data to alternating rows of the memory array; b) moving a read pointer through the array to read data from the alternating rows of the memory array in first-in, first-out order; and c) providing a half-full indication when the read pointer and the write pointer point to adjacent rows in the memory array. This method eliminates the need to route lines across the array to detect a half-full condition, thereby reducing die and power requirements and offering an increase in speed.

Abstract: A system is provided that enhances the interactivity of multimedia information in a closed cable network such as a hotel system or the like. The system includes a multimedia processing plurality of multimedia processing system, a telephone switching system, a video control system, a service operations platform, and a plurality of interactive devices. This system has the advantage of providing compression and/or transmission algorithms to maximize enhancement of the multimedia information. The system allows for enhanced interactivity within a closed cable system with minimum modification to the existing network.

Abstract: A method and apparatus as provided that simplifies the software required for modifying the contents of a register. By adding one gate to the register, a single command can be written to the register to modify the states of multiple bits. The system reduces software overhead significantly when multiple registers must be modified.