Abstract: A system provides for detection of enhanced capabilities of stations on a communications network. A specified pattern of link test pulses are detected and transmitted to provide for the indication of enhanced capabilities. This is particularly useful for determining whether a particular station is in full duplex or half duplex mode without affecting overall network performance.

Abstract: A system and method for increasing clock edge transition speed and edge phase accuracy. A split clock buffer provides separate controls of a pull-up transistor and a pull-down transistor. The buffer is off (high impedance) between clock edge transitions. Clock edge transition speed is improved by avoiding the transient condition of a conventional clock buffer where both of the pull-up and pull-down transistors are both on during clock edge transition.

Abstract: An incremental output current generation circuit is disclosed wherein a reference current and a reference voltage are established which follow a bias current which is then multiplied. A set of predetermined voltage reference points are established and the multiplied current supplied thereto. A ramping input voltage is compared to the established voltage referencing points by comparitors. The outputs of the comparators flag the highest voltage reference point which the value of the voltage exceeded. These outputs are sensed by a current generator thereby providing predetermined fractions of the reference current to be delivered at the output as the output source current. In such a manner, an incremental output source current is generated which is dependent on an input voltage level and predetermined incrementally by the value of an established reference current.

Abstract: A method for correcting over-corrected memory cells in a flash EPROM. The flash EPROM includes an array of memory cells (25), where each of the cells includes a gate 18, a floating gate (16), a source (12), a drain (14), and a substrate (10). The method includes bulk erasing each of cells in the array of cells (step 40), which results in a plurality of over-erased cells. The over-erased cells are then corrected (step 42), which results in a plurality of over-corrected cells. The over-corrected cells are identified (step 44) and selectively erased (step 46), such that a uniform threshold voltage distribution (54) is provided for the cells in the flash EPROM.

Abstract: An attenuated phase shift mask comprises a first layer having a thickness to provide a transmission in the range of about 3 to 10% formed on a transparent substrate and a second layer comprising a transparent material having a thickness to provide a desired phase shift, formed on said first layer. For a phase shift of 180.degree. and i-line wavelength (365 nm), where chromium is used as the first layer, then a thickness within the range of about 25 to 75 run is employed; where silicon dioxide is used as the second layer, then a thickness of about 400 to 450 nm is employed. While the oxide may be dry-etched, an isotropic wet etch provides superior aerial images.

Abstract: An input buffer circuit is disclosed which provides better noise margin and sharper switching edges than previously known systems. This circuit includes an input level translator, a Schmitt trigger circuit coupled to the input level translator circuit, a buffer, and sleep function circuit. The sleep function circuit reduces power when the input buffer circuit is powered down. The Schmitt trigger circuit comprises the hysteresis transfer characteristic providing means of the present invention. The Schmitt trigger circuit and buffer circuit, both with properly matched beta values for the participating transistors, allows for improved noise immunity of and sharper switching edges for the input buffer of the present invention.

Abstract: A circuit for allowing a memory module with an asymmetric addressing scheme to effectively operate with a memory controller which a symmetric address scheme is disclosed. The circuit includes a demultiplexer for receiving at least a last address bit from the memory controller and generating a plurality of control signals and a decoder. The decoder includes a plurality of decoder units. Each of the decoder units includes logic for receiving one of the plurality of control signals, a first strobe signal and a second strobe signal from the memory controller. Each of the decoder units also selectably provides a decoded second strobe signal responsive to the demultiplexer.

Abstract: An improved transistor design and methods of construction and testing for same. The novel transistor design method includes the steps of providing a transistor with multiple common gate areas; connecting each gate area to a pad; and adjusting the ratio of the area of the pad to the total of the gate areas to provide a predetermined ratio. The ratio may be adjusted by adjusting the size of the gate, in a single gate implementation, or adjusting the number of gates in a multiple gate configuration. The novel transistor includes a substrate, at least one source disposed on the substrate; at least one drain disposed on the substrate; and at least one gate disposed on the substrate between the source and the drain. The gate has a first layer of at least partially conductive material of area A.sub.g connected to a pad of area A.sub.p. In accordance with the present teachings, the antenna ratio R of the area of the pad A.sub.p to the area of the gate A.sub.g is a predetermined number.

Abstract: The present invention presents methods for reducing the discharge time of a Flash EPROM cell. In one aspect, a method includes the steps of forcing an ultraviolet voltage threshold, UVV.sub.t, below a discharge threshold voltage, V.sub.t. The method further comprises reducing the UVV.sub.t to about 0 V. Further, the method further comprises the step of reducing a core cell implant of a p-type dopant into a substrate of the cell. In a further aspect, a method for decreasing the discharge time includes the steps of providing a core cell implant of a p-type dopant into a surface of a substrate of the cell, and providing a surface doping of an n-type dopant into the core of the substrate, where the core implant reduces punchthrough and the surface doping of an n-type dopant reduces V.sub.t in the cell.

Abstract: A method for providing a secure local area network includes the steps of receiving a data packet having a destination address and comparing the destination address to stored end station addresses. The data packet is disrupted on the repeater for the ports except the port with an associated stored end station address matching the destination address. Also, the disrupting of the data packet can be enabled on an individual port basis. A system includes a controller, a memory/comparator, and an inverse disrupt control mechanism. The inverse disrupt control mechanism produces a disrupt signal to disrupt the data packet on non-matching ports of the repeater when a match occurs within the repeater. The data packet is not disrupted on a port linking two repeaters when there is no match within the repeater. The inverse disrupt control can also be enabled or disabled on an individual port basis.

Abstract: A storage element responsive to static and dynamic input signals which generates complementary static and dynamic output signals and incorporates scan test logic. The invention includes a first circuit for receiving dynamic and static input signals and providing static output signals in response thereto and a second circuit connected to the first circuit for providing dynamic output signals. In the illustrative embodiment, the first circuit includes a static flip-flop constructed with a multiplexer, a static input (master) latch and a static output (slave) latch. The static input latch provides first and second intermediate complementary outputs on first and second intermediate output terminals respectively.

Abstract: A handwriting signal processing front-end method and apparatus for a handwriting training and recognition system which includes non-uniform segmentation and feature extraction in combination with multiple vector quantization. In a training phase, digitized handwriting samples are partitioned into segments of unequal length. Features are extracted from the segments and are grouped to form feature vectors for each segment. Groups of adjacent from feature vectors are then combined to form input frames. Feature-specific vectors are formed by grouping features of the same type from each of the feature vectors within a frame. Multiple vector quantization is then performed on each feature-specific vector to statistically model the distributions of the vectors for each feature by identifying clusters of the vectors and determining the mean locations of the vectors in the clusters. Each mean location is represented by a codebook symbol and this information is stored in a codebook for each feature.

Abstract: A system for asynchronously duplexing direct access storage device (DASD) data in a plurality of DASD subsystems has the advantage of decoupling the data duplexing operation from the DASD write I/O operation. This ensures the write does not incur unnecessary wait states in the subsystem. By establishing a sequence checkpoint at which time a set of information packets are grouped together and processed as a single sequence unit, this decoupling and independent operation takes place. Through this independence, data copying to a secondary location can take place without affecting the performance of the subsystems and also not affecting the corresponding integrity of the data that is being updated.

Abstract: Short channel MOS devices are provided with two distinct doped polysilicon contacts: (a) doped polysilicon layers in contact with the source or drain regions (the LDD regions) and extending underneath the oxide region to abut the oxide liner of the trench sidewalls; and (b) polysilicon source and drain contacts in contact with the doped polysilicon layers. The shallow channel doping region is self-aligned with the lightly doped source and drain regions; this ensures vertically engineered profiles that give high punchthrough voltages and an excellent short channel control. The use of the doped polysilicon layers ensures self-alignment of source/drain diffusions and channel and prevents etching of TEOS in the trenches, which prevents exposure of trench sidewalls and formation of parasitic devices in the sidewalls. Further, use of doped polysilicon layers to form the LDD regions by diffusion results in high currents and shallow junctions.

Abstract: An arbitrary pattern write head assembly for writing timing-based servo patterns on magnetic storage media is provided, comprising: (a) a first pole piece comprising a substrate comprising a magnetic material, said substrate having a major surface; (b) a plurality of electrically conducting windings formed on the major surface; and (c) a second pole piece formed on the substrate, with a portion thereof formed above the plurality of electrically conducting windings and electrically insulated therefrom, the second pole piece having at least one opening therethrough defining a gap above the electrically conducting windings and the substrate, the second pole piece comprising at least two layers, each layer comprising a magnetic material. A method of batch fabricating servo writer heads is also provided for batch fabrication of servo writer heads at a very low cost. The method enables fabrication of heads capable of azimuthal recording commonly practiced in the video recording art.

Abstract: Computation-intensive applications such as sensor signal processing, sensor fusion, image processing, feature identification, pattern recognition, and early vision place stringent requirements on the computational capacity, size, weight, and power dissipation of modular computational systems intended for both embedded and high performance computer environments. Such ultra high speed, ultra high density computational modules will typically be configured with multiple processor, memory, dedicated sensor, and digital signal processing chips in close-packed multichip modules. The present invention relates to a novel architecture and associated apparatus for the development of highly multiplexed photonic interconnections between pairs of such electronic chips incorporated in vertical stacks within three-dimensional multichip module configurations.

Abstract: A control system for dynamically regulating an operating condition of a device used with and controlled by a host computer system. The inventive system includes a sensor arrangement for detecting the desired operating condition of the device and providing a signal in response thereto. A control system dynamically regulates the operation of the device in response to commands generated by the host system and the sensor output signal to maintain the operating condition of the device within predetermined parameters. In a particular implementation, the advantageous teachings of the present invention are incorporated in an optical drive system. One or more sensors are used to detect the operating temperature of the drive and provide an analog output signal in response thereto. The signal is digitized and input to a microprocessor based control circuit.

Abstract: A non-invasive self-contained functional electrical stimulation garment is disclosed. The garment, which is preferably in the form of a glove, may be donned in one piece by a user of reduced motor ability e.g. a person exhibiting hand tremors or who is a quadriplegic, paraplegic or hemiplegic. The garment is preferably made of a perforated elastic material and being adapted to fit over a part of said user's body. The garment has electrical connections internal to the garment that are adapted to make electrical contact with self-adhesive skin electrodes on the user. A joint movement sensor and a battery-driven electronic controller-stimulator located on the garment, with the electrical connections, sensor and controller-stimulator being electrically and cooperatively interconnected. In the form of a glove, the garment can permit a user of reduced motor ability to grip objects.

Abstract: A system and device is provided that enhances the interactivity of multimedia information across a communications network or in combination with other networks including telecommunication and cable broadcasting. The system includes an interactive multimedia mastering (IMM) system for receiving multimedia program materials from a program source, a multimedia call processing system (MCPS) coupled to the IMM, and a plurality of interactive multimedia devices (IMDs) for distributing multimedia information to users. The IMM optimizes the program materials by separating the information into primary and secondary layers using psychographic parameters to differentiate between important and less important multimedia information, and then compresses at least a portion of the layers for transmission to the MCPS. The IMDs accept user commands for multimedia information from a telephone, which cause the IMD to transmit a control signal to the MCPS.