Abstract: A removable, reusable, wrap-around cover for a paperback book consisting of a single sheet of semi-rigid synthetic plastic material, vertically scored with multiple lines to allow it to fit around varying thickness of book, with two pairs of flaps on each side and a single loop of elastic at the center of the sheet. The main sheet wraps around the covers and spine of the book, and folds over the edges of the front and rear covers to keep the cover on the book. The flaps are formed such that when the main sheet has been folded around the book, they can be folded onto the insides of the covers and linked together so that the two pairs of flaps form a pair of bands that keeps the edges of the main sheet folded around the covers of the book. The elastic loop stretches around the entire assembled cover and book, and keeps the book shut to protect it from damage.

Abstract: A memory controller is provided in which the address path is disabled by a sequencer to reduce power consumption when the sequencer is in an IDLE mode. When access is requested by the bus, the sequencer changes into an ALERT mode, thereby enabling the address path. Subsequently the sequencer then changes into an EXECUTE mode to perform data transfer operations. After the transfer is completed, the sequencer returns to the ALERT mode and an inactive time counter begins counting. If no access is requested before the counter reaches a predetermined number of counts, the sequencer returns to the IDLE mode and the address path is disabled to save power. However, if another cycle request occurs while in the ALERT mode, the EXECUTE mode is entered into immediately.

Abstract: A system and method for efficiently charging and discharging a capacitive load from a single voltage source. The system includes a first switch for selectively connecting the voltage source to the load and a second switch for selectively providing a short across the load as may be common in the art. A particularly novel aspect of the invention resides in the provision of plural capacitive elements and a switching mechanism for selectively connecting each of the capacitive elements to the load whereby the load is gradually charged or discharged. In the illustrative embodiment, the switching mechanism includes a set of switches for selectively connecting each of the capacitive elements to the capacitive load and a switch control mechanism for selectively activating the switches.

Abstract: Capacitance between metal interconnects electrically contacting metal contacts in semiconductor devices comprising doped regions contacted by the metal contacts surrounded by a first interlevel dielectric layer is reduced by (a) electrically contacting a first group of the metal contacts with a first group of first metal interconnects and electrically contacting a second group of the metal contacts with a second group of first metal interconnects, the first metal interconnects formed on a first level and surrounded by a second interlevel dielectric layer; and (b) electrically contacting the second group of first metal interconnects with second metal interconnects by means of metal plugs, the metal plugs surrounded by the second interlevel dielectric layer, and the second metal interconnects surrounded by a third interlevel dielectric layer.

Abstract: A CPVC adhesive for joining CPVC pipes comprises: (a) about 18 to 28 wt % CPVC resin; (b) a high vapor pressure solvent comprising about 15 to 35 wt % tetrahydrofuran and 0 to about 30 wt % methyl ethyl ketone; and (c) a low vapor pressure solvent comprising about 20 to 45 wt % cyclohexanone, 0 to about 30 wt % N-methyl pyrrolidone, and 0 to 10 wt % dibasic esters (a mixture of refined dimethyl esters of adipic, glutaric, and succinic acids). The VOC level of the CPVC adhesive composition of the invention is at or below the allowed maximum value of 450 g/l, yet the adhesive meets or exceeds required performance standards, such as hydrostatic burst strength and hydrostatic sustained pressure test.

Abstract: A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

Abstract: A circuit is provided that allows for the substitution of a memory module with one type of addressing scheme with a second memory module which has a different type of addressing scheme. Through the use of a row address strobe (RAS) generator and address generator which receives multiple RAS signals, a new RAS signal is generated that is in accordance with the one type of addressing scheme and an address signal is provided which indicates which portion of the memory is to be accessed.

Abstract: A system for interactive multimedia entertainment that stores a plurality of video and/or songs and allows for the receipt of information concerning the cost of each song and other relevant information. The system has application to music listening, video entertainment and Karaoke entertainment systems.

Abstract: A timing recovery scheme disposed to be substantially invariant to the specific composition of an input data sequence. The phase detection network of the present invention will typically be addressed by a data waveform having a plurality of data packets separated by data delimiters. In operation, the phase detection network of the present invention generates a phase error signal in response to the phase difference between a binary data waveform and a periodic clock waveform recovered therefrom. The inventive phase detection network includes a shift register for storing samples of the incident data waveform. The contents of the shift register are monitored by a boundary detection circuit disposed to signal the presence of one of the delimiters within the shift register. Upon detection of such a delimiter a boundary correction circuit is disposed to generate a phase detection enable signal.

Abstract: A fused glass block having an axial gradient index of refraction profile between two opposed parallel surfaces, with a change in refractive index from one of the surfaces to the other ranging from about 0.04 to 0.47, is provided. The fused glass block has a change in thermal expansion coefficient from one of the surfaces to the other of less than about 3.times.10.sup.-7 .degree.C..sup.-1, has essentially no strain or birefringence therein, and has a smoothly varying refractive index profile from one of the surfaces to the other. The fused glass block is prepared from at least two pre-selected compositions of a lead-silicate glass series that has been discovered to provide the requisite properties.

Abstract: An improved nonvolatile memory device is provided, in which the threshold voltage variations (V.sub.ts) and transconductance degradation are significantly reduced. The NVM includes protection structure for limiting the process induced damage incurred during the manufacturing process. The protection structure is utilized to provide reliable and stable dielectrical characteristics for the NVM device. The protection structure is easy to implement and will not affect the conventional NVM performance.

Abstract: Metal pillars (18) having diameters of less than about 1.0 .mu.m are grown in vias (16) in dielectric layers (14) between metal layers (12, 22) by a process comprising: (a) forming a first metal layer (12) at a first temperature and patterning the metal layer; (b) forming the dielectric layer to encapsulate the first patterned metal layer, the dielectric layer having a compressive stress of at least about 100 MegaPascal and being formed at a second temperature; (c) opening vias in the dielectric layer to exposed underlying portions of the patterned metal layer, the vias being less than about 1.0 .mu.m in diameter; (d) heating the semiconductor wafer at a temperature that is greater than either the first or second temperatures to induce growth of metal in the vias from the metal layer; and (e) forming the second metal layer (22) over the dielectric layer to make contact with the metal pillars.

Abstract: A local interconnect silicide structure (30) for connecting silicon regions (16) to silicon regions (20) separated by oxide regions (24) comprises a first portion of titanium silicide/titanium nitride/titanium silicide contacting the silicon regions and a second portion of titanium/titanium nitride/titanium silicide contacting the oxide regions. The silicide structure is also useful for connecting source/drain regions (14) and polysilicon interconnects (28). Two separate heating steps are employed, separated by an etch step to form the interconnects (34, 36). The first heating step forms (a) titanium silicides with single or polycrystalline silicon, using a first titanium layer (30a) at the bottom of the silicide structure and (b) titanium silicides with amorphous silicon (30d), using a second titanium layer (30c) on top of the titanium nitride layer (30b) on which the amorphous silicon is deposited and then patterned.

Abstract: A frame buffer architecture for a graphics controller provides for conversion of cathode ray tube (CRT) data streams to multi-segment data streams. The buffer architecture operates such that the CRT frame rate is the same as the multi-segment frame rate. In so doing, a graphics controller can operate within its intended specification while operating at the same clock frequency whether in CRT or multi-segment mode. In addition, this architecture overcomes the other problems associated with prior art graphics controllers.

Abstract: An apparatus and method for unwrapping an article (e.g., bread) wrapped in a package having a first end and a second end. The inventive apparatus includes a first mechanism for holding the first end of the package, a second mechanism for at least partially opening the second end of the package, and a third mechanism for removing the article from the package. In a specific implementation, package is supported on a conveyor, the retaining clip on the package is engaged by a guide and the package is moved into contact with a blade which cuts substantially through the package. The package is held by the guide while the article falls from the package due to the effect of gravity.

Abstract: A multiphase clock generator which exhibits frequency stability in the presence of power supply noise. The clock generator of the present invention includes a phase detector for generating a phase error signal in response to the phase difference between an input signal and a recovered clock signal. A phase-locked feedback loop is operative to synthesize a recovered clock signal in response to the phase error signal. Included within the feedback loop is a differential ring oscillator disposed to provide first and second phase-shifted output signals at first and second output ports. The addition of a combination network to the multiphase clock generator of the present invention allows a multiplied clock signal to be derived from an input signal. Specifically, the phase-locked feedback loop 18 included within the clock multiplier of the present invention provides a plurality of sequentially phase-shifted waveforms at a first multiple of the frequency of the input signal.

Abstract: A storage controller having additional cache memory and a system for recovering from failure and reconfiguring a control unit thereof in response thereto. The inventive controller includes a first cluster for directing data from a host computer to a storage device and a second cluster for directing data from a host computer to a storage device. A first cache memory is connected to the first cluster and a second cache memory is connected to the second cluster. A first nonvolatile memory is connected to the second cluster and a second nonvolatile memory is connected to the first cluster. Data is directed to the first cache and backed up to the first nonvolatile memory. The second cache is similarly backed up by the second nonvolatile memory. In the event of failure of the first cache memory, data is directed to the second cache and backed up in the second nonvolatile memory.

Abstract: A system for accurately measuring current drawn intermittently by an inductive load over a time interval T including a first and a second time subinterval during which the load is in state S1 and state S2 respectively and drawing current and a third time subinterval during which the load is in state S3, an idle state, and drawing substantially zero current is provided. In a preferred embodiment, the current measuring system includes a pilot current detection circuit having a pulse width modulator which generates a 1/2T.sub.1 timing signal representing the average amplitude of the current drawn by the load while in states S1 and S2. A correction circuit generates a logic signal that indicates the time of transition of the inductive load from state S2 to state S3 and from state S3 to state S1. The logic signal is used to clock a first sample and hold circuit to provide a scaling factor utilized to correct the average load current.

Abstract: An asynchronous video system provides for the appropriate pixel data to be displayed. The system maps display control signals into a memory clock while maintaining the appropriate relationship with pixel data. Therefore, the display control signals are generated using the memory clock. Hence, no synchronization circuit is necessary to ensure that the memory control circuit and display control circuit are running at the same frequency.