Patents Represented by Attorney, Agent or Law Firm Bever, Hoffman & Harms, LLP
  • Patent number: 8020123
    Abstract: Apparatus and method for transaction-based abstraction process can, in an embodiment, include three main phases: first, selecting a set of transaction-processing finite state machines (FSMs) that determine transaction boundaries. Second, extracting the transaction-processing FSMs, composing them, and computing an abstracted FSM corresponding to the composed FSM after abstraction, step 115. Third, abstracting all signals in the design based on the computed abstract FSM.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: September 13, 2011
    Assignee: Synopsys, Inc.
    Inventor: James Christopher Wilson
  • Patent number: 8018003
    Abstract: A field effect transistor includes a source region and a drain region in contact with a channel region. The source and drain regions are formed in insulating pockets that cause the source and drain regions to be electrically isolated from the substrate, thereby minimizing junction capacitance and device crosstalk. The structures that define the insulating pockets can be insulating layers formed in one or more wells in the substrate, or can be a blanket insulating formed over the substrate in which a well is formed to contain the transistor.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: September 13, 2011
    Assignee: Synopsys, Inc.
    Inventor: Chandrashekhar V. Patil
  • Patent number: 8019369
    Abstract: Transient distortion is compensated for by multiplying an exponentially-decaying phase shift onto the distorted waveform. The exponentially decaying phase shift waveform is patterned after the transient which typically takes the form of an exponential and occurs upon introduction of power to a circuit or circuit component. A digital circuit produces an appropriate exponentially-decaying waveform which is used as the input for a look up table whose output is a complex sinusoidal waveform capable of compensating for the distortion. The complex sinusoid is multiplied onto the transmitted waveform. The decaying exponential is biased so that it crosses a threshold at which point the compensating circuitry is turned off.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: September 13, 2011
    Assignee: Qualcomm Atheros, Inc.
    Inventors: Paul J. Husted, Bevan M. Baas
  • Patent number: 8014305
    Abstract: Transmission monitoring can be used to determine the optimum data rate for a channel. The transmission monitoring can include sending data packets in the channel using various data rates. At least some data packets are sent using the current optimum data rate, a rate lower than the current optimum data rate, and a rate higher than the current optimum data rate. One of these data rates can be selected as the new optimum data rate. In one embodiment, if the current optimum data rate is less than a predetermined data rate, then the client is triggered to begin scanning for other available access points.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: September 6, 2011
    Assignee: Qualcomm Atheros, Inc.
    Inventors: Jeffrey M. Gilbert, James Woo
  • Patent number: 8010072
    Abstract: A technique for improving frequency synthesizer performance by frequency-compensating charge pump current in order to maintain a consistent loop bandwidth over a wide operating frequency range is described. A relationship between the capacitance value associated with a voltage controlled oscillator resonant tank and the magnitude of current pulses in a related charge pump is exploited to bound the loop bandwidth of the frequency synthesizer over both operating frequency and process variation. A control state machine generates digital coarse tune values that dynamically select a capacitance for the resonant tank, such that the voltage controlled oscillator operates within an optimal control voltage range. Each dynamically selected capacitance value is then used to determine the magnitude of current pulses in the charge pump.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: August 30, 2011
    Assignee: Atheros Communications, Inc.
    Inventor: Lalitkumar Nathawad
  • Patent number: 8000227
    Abstract: Current OFDM systems use a limited number of symbols and/or sub-channels to provide approximations for channel estimations and pilot tracking, i.e. phase estimations. For example, two training symbols in the preamble of a data packet are used to provide channel estimation. Four of the fifty-four sub-channels are reserved for providing phase estimation. However, noise and other imperfections can cause errors in both of these estimations, thereby degrading system performance. Advantageously, decision feedback mechanisms can be provided to significantly improve channel estimation and pilot tracking in OFDM systems. The decision feedback mechanisms can use data symbols in the data packet to improve channel estimation as well as data sub-channels to improve pilot tracking.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: August 16, 2011
    Assignee: Atheros Communications, Inc.
    Inventors: Qinfang Sun, Won-Joon Choi, Jeffrey M. Gilbert, Ning Zhang, Yi-Hsiu Wang, Tao-Fei Samuel Ng
  • Patent number: 7997680
    Abstract: Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features, and by printing each design layer using individual print solution droplets deposited onto the substrate. A printhead alignment operation includes positioning the printhead and printing a spot onto the substrate from each ejector, determining a vertical offset between an expected location of each spot along a vertical axis and the actual location of the spot along the vertical axis, calculating a linear fit line for the vertical offset of each spot plotted against an expected location of the spot along a horizontal axis, calculating the slope of the linear fit line, and rotating the printhead relative to the substrate according to an angle defined by the slope of the linear fit line.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: August 16, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Steven E. Ready, William S. Wong
  • Patent number: 7999175
    Abstract: Interdigitated back contact (IBC) solar cells are produced by depositing spaced-apart parallel pads of a first dopant bearing material (e.g., boron) on a substrate, heating the substrate to both diffuse the first dopant into corresponding first (e.g., p+) diffusion regions and to form diffusion barriers (e.g., borosilicate glass) over the first diffusion regions, and then disposing the substrate in an atmosphere containing a second dopant (e.g., phosphorus) such that the second dopant diffuses through exposed surface areas of the substrate to form second (e.g., n+) diffusion regions between the first (p+) diffusion regions (the diffusion barriers prevent the second dopant from diffusion into the first (p+) diffusion regions). The substrate material along each interface between adjacent first (p+) and second (n+) diffusion regions is then removed (e.g.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: August 16, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Kenta Nakayashiki, Baomin Xu
  • Patent number: 8001397
    Abstract: A method of allocating power to ports in an Ethernet switch, including: (1) determining the available capacity of a power pool used to supply the ports, (2) assigning a configuration power to each of the ports, (3) selecting a port to be enabled, (4) determining whether the available capacity of the power pool exceeds the configuration power assigned to the selected port, and, if the available capacity of the power pool exceeds the configuration power assigned to the selected port, then (4) subtracting the configuration power assigned to the selected port from the available capacity of the power pool, (5) enabling and powering the selected port and simultaneously detecting whether the selected port is connected to a powered device, and (6) adding the configuration power assigned to the selected port to the available capacity of the power pool if the port is not connected to a powered device.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: August 16, 2011
    Assignee: Foundry Networks, LLC
    Inventor: Rakesh Hansalia
  • Patent number: 7995380
    Abstract: A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: August 9, 2011
    Assignee: Synopsys, Inc.
    Inventor: Tsu-Jae King Liu
  • Patent number: 7996200
    Abstract: A method for transaction-based abstraction allows a comprehensive test plan to be automatically generated for a hardware design, where the test plan comprises a set of coverage points derived based on a signal classification created using transaction-based analysis to identify the architecturally-visible state of the design, using heuristic techniques to identify finite-state machines (FSMs) in a design that processes transactions, from which transaction boundaries can be identified, and wherein signals are classified based on the abstracted design as either transient, temporary, or persistent for use in developing the test plan.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: August 9, 2011
    Assignee: Synopsys, Inc.
    Inventor: James C. Wilson
  • Patent number: 7992958
    Abstract: Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features, and by printing each design layer using individual print solution droplets deposited onto the substrate. A printhead alignment operation includes printing a first spot from a first printhead ejector on a first substrate location, positioning a second ejector over the first substrate location and printing a second spot, measuring a distance between the first spot and the second spot, adjusting a rotational orientation between the print head and the substrate to reduce the distance between the first spot and the second spot, and then repeating the printing, measuring and adjusting processes until the first and second spots are separated by a predefined threshold value apart. The design layers are then printed.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: August 9, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Steven E. Ready, William S. Wong
  • Patent number: 7995547
    Abstract: A system and method are described for repeatedly and efficiently performing a wireless communication channel survey to determine whether comparable communications devices exist, which frequencies are in use, and the identities of the comparable communications devices. A beacon data table stores received beacon data which is used to predict beacon arrival times, thereby allowing a receiver to be tuned away from an active data communications channel for a shorter dwell time than a beacon period. A further efficiency can be gained if beacon generators cooperatively stagger their beacon times according to one or more measurable characteristics of the beacon generator, e.g. the operating channel number and the SSID.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: August 9, 2011
    Assignee: Atheros Communications, Inc.
    Inventor: Craig H. Barratt
  • Patent number: 7988061
    Abstract: A portable card adapted to interact with a data processing station when the portable card and the data processing station are moved relative to each other is disclosed. The portable card includes a substrate having a predetermined shape, e.g. rectangular. An accessible embedded storage member is enclosed within said substrate. The storage member includes at least one layer of storage material for storing information in a predetermined format for processing by the data processing station. The storage member and the substrate are adapted to be transported relative to each other to expose at least a portion of the storage member to the data processing station to facilitate processing of stored information and for embedment of the storage member within the substrate. The storage member may be in the form of an elongated strip member, or a circular member.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: August 2, 2011
    Assignee: UltraCard, Inc.
    Inventors: Bert D. Cook, Jr., Donald C. Mann
  • Patent number: 7988036
    Abstract: A portable card adapted to interact with a data processing station when the portable card and the data processing station are moved relative to each other is disclosed. The portable card includes a substrate having a predetermined shape, e.g. rectangular. An accessible embedded storage member is enclosed within said substrate. The storage member includes at least one layer of storage material for storing information in a predetermined format for processing by the data processing station. The storage member and the substrate are adapted to be transported relative to each other to expose at least a portion of the storage member to the data processing station to facilitate processing of stored information and for embedment of the storage member within the substrate. The storage member may be in the form of an elongated strip member, or a circular member.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: August 2, 2011
    Assignee: UltraCard, Inc.
    Inventors: Bert D. Cook, Jr., Donald C. Mann
  • Patent number: 7985081
    Abstract: A method for mounting the micro spring structures onto cables or contact structures includes forming a spring island having an “upside-down” stress bias on a first release material layer or directly on a substrate, forming a second release material over at least a portion of the spring island, and then forming a base structure over the second release material layer. The micro spring structure is then transferred in an unreleased state, inverted such that the base structure contacts a surface of a selected apparatus, and then secured (e.g., using solder reflow techniques) such that the micro spring structure becomes attached to the apparatus. The spring structure is then released by etching or otherwise removing the release material layer(s).
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: July 26, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Koenraad Van Schuylenbergh, Thomas Hantschel
  • Patent number: 7984395
    Abstract: A method of increasing hierarchy compression of a metal 1 standard cell layout during optical proximity correction (OPC) is provided. This method can use a context determination defined from the outermost OPC correctable-edge boundaries of a metal 1 standard cell and not extending past outermost OPC correctable edge boundaries of adjacent metal 1 standard cells in other rows. The method can also include (or can alternatively include) adjusting the landing pads (resulting from metal 2 placement) to fit within the lines of the metal 1 standard cell layout. This adjusting can be performed by a place and route tool as part of a “clean-up” operation after metal 2 placement. The landing pads can be sized for single or double vias. A layout design for the metal 1 standard cell layout can be output based on using the context determination and/or adjusting the landing pads for hierarchy compression.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: July 19, 2011
    Assignee: Synopsys, Inc.
    Inventor: Christopher M. Cork
  • Patent number: 7980195
    Abstract: A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: July 19, 2011
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Michael L. Chabinyc, Ana C. Arias
  • Patent number: 7982546
    Abstract: A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N?1).
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: July 19, 2011
    Assignee: Atheros Communications, Inc.
    Inventor: Michael P. Mack
  • Patent number: 7982518
    Abstract: A timing circuit for generating asynchronous signals is provided that uses minimal area while maximizing speed. This timing circuit can include a timing control block and disable/enable circuitry. The timing control block can include an SR latch and first and second delay blocks. The SR latch can generate first and second signals, wherein the first and second signals are asynchronous. The first delay block can generate a delayed first signal and provide that signal to a first input terminal of the SR latch. Similarly, the second delay block can generate a delayed second signal and provide that signal to a second input terminal of the SR latch. Notably, the first and second delay blocks delay positive going edges of the first and second signals differently than negative going edges of the first and second signals.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: July 19, 2011
    Assignee: Atheros Communications, Inc.
    Inventor: Brian J. Kaczynski