Abstract: A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.

Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.

Abstract: A method of controlling fluid through a layer of a soft compressible (e.g., gel) material including an array of fluid flow paths. The fluid flow paths are normally open, allowing fluid flow. An electric field is applied in regions where fluid flow is undesirable. The electric field compresses the material closing the flow path thereby preventing further fluid flow.

Abstract: An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators. A software debugger interface permits a software application to be loaded and executed on the virtual embedded system. A virtual test bench may be coupled to the simulation to serve as a human-machine interface. In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project. IP components, such as processor cores, may be evaluated using a virtual embedded system. In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system.

Abstract: A delta-sigma fractional-N frequency synthesizer having a charge pump with error canceling circuitry eliminates a non-linear term from the charge pump transfer function. The charge pump includes a matched pair of charging current sources, each supplying a first current IP1 to a common node, when enabled. The charge pump also includes a matched pair of discharging current sources, each sinking a second current IN1 from the common node, when enabled. The error canceling circuitry includes a charging current source, which supplies a current equal to the second current IN1 to the common node, when enabled. The error canceling circuitry also includes a discharging current source, which sinks a current equal to the first current IP1 from the common node, when enabled. The charging and discharging current sources of the error canceling circuitry are both enabled when either one of the matched pairs of charging and discharging current sources is enabled.

Abstract: Printing systems are disclosed that produce homogenous, smooth edged printed patterns (such as integrated circuit (IC) patterns) by separating pattern layouts into discrete design layers having only parallel layout features. By printing each design layer in a printing direction aligned with the parallel layout features, the individual print solution droplets deposited onto the substrate do not dry before adjacent droplets are deposited. Therefore, printed patterns having accurate geometries and consistent electrical properties can be printed.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Abstract: A solar cell production system utilizes self-contained vacuum chucks that hold and cool solar cell wafers during transport on a conveyor between processing stations during a fabrication process. Each self-contained vacuum chuck includes its own local vacuum pump and a closed-loop cooling system. After each wafer is processed, it is removed from its vacuum chuck, and the vacuum chuck is returned to the start of the production line by a second conveyor belt. In one embodiment, each vacuum chuck includes an inductive power supply that is inductively coupled to an external source to drive that vacuum chuck's vacuum pump and cooling system. An optional battery is recharged by the inductive power supply, and is used to power the vacuum pump and cooling system during hand-off between adjacent processing stations.

Abstract: To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.

Abstract: A class D amplifier includes a noise-shaping modulator, a pulse width modulator, and a pulse amplifier. The noise-shaping modulator receive a pulse code modulated (PCM) signal and produces an oversampled PCM signal. The pulse width modulator produce a pulse width modulated (PWM) signal from the oversampled PCM signal. The pulse amplifier amplifies the PWM signal to produce an amplified PWM signal. The PWM uses a lookup table to convert from PCM to PWM. A compensation circuit optimizes amplifier performance. An optional demodulator filter converts the amplified PWM signal to an analog signal. The amplifier is ideal for integrated audio applications.

Abstract: An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C150, a second portion extending into an enlarged drain diffusion area D150 away from the channel region, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitance. The width of the floating gate extension portion is minimized, while both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. HV LDD implant in the NVM transistor is replaced by LV LDD. The floating gate is formed using substantially U-shaped or J-shaped polysilicon structures. Various array addressing schemes are disclosed.

Abstract: A portable memory card including a molded plastic casing formed over a memory device and other circuits mounted on a substrate such that the molding material extends over side edges of the substrate to provide accurate width and thickness dimensions. Contact pads are formed on a lower surface of the PCBA substrate, which is exposed through a bottom of the casing. The PCBA is fabricated on a substrate carrier, then positioned inside of a mold assembly. During the molding process, a rod extends from an upper portion of the mold assembly and pushes the substrate against the lower surface. A vacuum is then applied to hold the substrate against the lower surface of the mold, and the rod is subsequently withdrawn from the mold cavity during injection of the molten molding material. A single cavity mold assembly provides molding material extends over front and back edges of the memory card.

Abstract: A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (IREF).

Abstract: A flash memory device includes one or two panels that are attached solely by a thermal bond adhesive to either a frame or integrated circuits (e.g., flash memory devices) disposed on a PCBA. The frame is disposed around the PCBA and supports peripheral edges of the panels. The thermal bond adhesive is either heat-activated or heat-cured, and is applied to either the memory devices, the frame or the panels, and then compressed between the panels and flash memory devices/frame using a fixture. The fixture is then passed through an oven to activate/cure the adhesive. An optional insulating layer is disposed between the panels and the ICs. An optional conforming coating layer is formed over the ICs for preventing oxidation of integrated circuit leads or soldering area, covering or protecting extreme temperature exposure either cold or hot, and waterproofing for certain military or industrial applications.

Abstract: A 3-D optical microscope, a method of turning a conventional optical microscope into a 3-D optical microscope, and a method of creating a 3-D image on an optical microscope are described. The 3-D optical microscope includes a processor, at least one objective lens, an optical sensor capable of acquiring an image of a sample, a mechanism for adjusting focus position of the sample relative to the objective lens, and a mechanism for illuminating the sample and for projecting a pattern onto and removing the pattern from the focal plane of the objective lens. The 3-D image creation method includes taking two sets of images, one with and another without the presence of the projected pattern, and using a software algorithm to analyze the two image sets to generating a 3-D image of the sample. The 3-D image creation method enables reliable and accurate 3-D imaging on almost any sample regardless of its image contrast.

Abstract: A press-push type computer peripheral “flash drive” device includes an elongated (e.g., metal) tubular casing containing a PCBA having a plug connector. A plastic housing assembly includes front and rear cap portions mounted over the open ends of the tubular casing, and a fixed plastic sleeve portion disposed in the tubular casing. The PCBA is secured to a plastic sliding rack structure that is disposed in the tubular casing and includes an actuating button protruding through a slot formed in a wall of the tubular casing. When the actuating button is manually pushed and slid along the slot, a portion of the sliding rack structure slides against the plastic sleeve portion in deploying and retracting the USB connector out of the device.

Abstract: The present invention relates to a mixed mode electronic circuit that implements a PLL cell that employs an auto-range algorithm to lock to a wide range of input reference signals.

Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

Abstract: To provide an extra wide bandwidth communication using standard channels, multiple non-overlapping channels can be used. To provide a 40 MHz communication, two non-overlapping 20 MHz channels, i.e. a control channel and an extension channel, can be used to provide an effective 40 MHz channel. Advantageously, a wireless device can dynamically detect 20/40 MHz signals on a packet-by-packet basis, thereby facilitating commercially viable 40 MHz communication. The wireless device can monitor traffic on the extension channel to facilitate accurate 20/40 MHz decision making. Protection, e.g. legacy preambles and RTS/CTS headers, can be provided on the control and extension channels.

Abstract: Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.