Abstract: Methods and apparatus are provided for harnessing the effects of process variations in a semiconductor device. In one example, implementing an electronic design based on collected performance parameters is provided. In general, a core is segmented into multiple core regions. A performance parameter can be collected from each of the core regions. The performance parameter can be collected with a performance measuring mechanism associated with the core region. The performance parameter can be correlated to the performance requirements of an electronic device portion, and the electronic design portion can be implemented in a core region that has a performance parameter matched to the needs of the electronic design portion. In this way, process variation effects are harnessed by optimizing the implementation of the electronic design in regions of the semiconductor device best suited the needs of each electronic design portion. Therefore, performance/power optimization of the semiconductor device can be realized.
Abstract: A fluid-filled vibration damping device including: a rubber elastic body elastically connecting a first and second mounting member and partially defining a pressure-receiving chamber filled with a non-compressible fluid; a flexible layer partially defining an equilibrium chamber filled with the non-compressible fluid; an orifice passage permitting a fluid communication between the pressure-receiving chamber and equilibrium chamber; and a cushion surface situated opposite to an opening of the orifice passage to the pressure-receiving chamber in a first direction of flow of the fluid into and out of the opening, with a predetermined distance therebetween, while extending in a second direction approximately perpendicular to the first direction.
Abstract: Ionic emission electrostatic device (1) for depositing on the surface (sp) of a multitude of aerosol particles (p1, p2, . . . , pn) within a fluid (F), a quasi-homogeneous quantity of ions (iq). This electrostatic device (1) is constituted by a conductive discharge corona electrode (EC) and a noncorona conductive receptor electrode (ER). The pseudo-planar active face (SA) of its receptor electrode (ER) is covered by a plurality of craters with sharp edges, in a closed pseudo circle, exhibiting on their end edges (Ai) a section of minimum bend radius, and enclosing the orifices (O1, O2, . . . , On) and terminating towards the outside of the active face (SA). The craters are distributed quasi-uniformly on the active face (SA), in its two geometric directions. The surface flow of ions (iq) originating from the corona electrode (EC) and in the direction of the active face of the receptor electrode (ER) has an increased homogeneity.
Type:
Grant
Filed:
December 17, 2001
Date of Patent:
April 3, 2007
Assignee:
Airinspace Limited
Inventors:
Jean-Marie Billiotte, Alexandre Vladimirovitch Nagolkin, Frédéric Basset, Elena Vladimirovna Volodina
Abstract: Improved techniques for determining Java hashcode values for Java objects are disclosed. The techniques can be implemented to use a new Java Bytecode instruction which is suitable for execution by a Java virtual machine. As such, the new Java Bytecode instruction can be executed to determine Java hashcode value. Moreover, as will be appreciated, the Java hashcode values can be determined without invoking the Java method which is conventionally used to determine hashcode values. This means that the costly overhead associated with repeatedly invoking Java methods is avoided. In other words, operations that are conventionally performed each time this method is invoked need not be performed. As a result, the performance of virtual machines, especially those operating with limited resources (e.g., embedded systems), can be improved.
Abstract: A method for forming damascene features in a dielectric layer over a barrier layer over a substrate is provided. A plurality of vias are etched in the dielectric layer to the barrier layer with a plasma etching process in the plasma processing chamber. A patterned photoresist layer is formed with a trench pattern. Within a single plasma process chamber a combination via plug deposition to form plugs in the vias over the barrier layer and trench etch is provided.
Type:
Grant
Filed:
June 24, 2003
Date of Patent:
March 20, 2007
Assignee:
Lam Research Corporation
Inventors:
Sean S. Kang, Sangheon Lee, Wan-Lin Chen, Eric A. Hudson, Reza Sadjadi
Abstract: A method and an apparatus for performing the method of decoding and playing in reverse MPEG encoded content. The MPEG encoded content comprises a plurality of pictures frames. The picture frames are comprised of one or more picture frame types selected from the group of picture frame types including I-frames, P-frames, and B-frames. The method and the apparatus for performing the method comprise the steps of obtaining a group of MPEG picture frames (“GOP”), determining the total number of picture frames in the GOP, and setting an index value equal to the total number of picture frames in the GOP. Next, a picture frame F that has a display order equal to the index value is decoded and displayed, and the earliest B-frame that depends upon frame F is determined. All the B-frames that depend upon frame F are decoded and displayed from highest display order to lowest display order, and the index value then is set to a value equal to one less than the display order of the earliest B-frame that depends upon frame F.
Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.
Type:
Grant
Filed:
August 31, 2004
Date of Patent:
March 13, 2007
Assignee:
LSI Logic Corporation
Inventors:
Mohammad R. Mirbedini, Venkatesh P. Gopinath, Hong Lin, Verne Hornback, Dodd Defibaugh, Ynhi Le
Abstract: The invention described herein provides systems and methods for multi-modal imaging with light and a second form of imaging. Light imaging involves the capture of low intensity light from a light-emitting object. A camera obtains a two-dimensional spatial distribution of the light emitted from the surface of the subject. Software operated by a computer in communication with the camera may then convert two-dimensional spatial distribution data from one or more images into a three-dimensional spatial representation. The second imaging mode may include any imaging technique that compliments light imaging. Examples include magnetic resonance imaging (MRI) and computer topography (CT). An object handling system moves the object to be imaged between the light imaging system and the second imaging system, and is configured to interface with each system.
Type:
Grant
Filed:
June 29, 2004
Date of Patent:
March 13, 2007
Assignee:
Xenogen Corporation
Inventors:
Michael D. Cable, Bradley W. Rice, David Nilson
Abstract: Methods for forming a diffusion barrier on low aspect features of an integrated circuit include at least three operations. The first operation deposits a barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features of the integrated circuit. The second operation deposits barrier material to provide some minimal coverage over the bottoms of the recessed features. The third operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of the recessed features, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.
Abstract: Methods and apparatus are described for distributing gaming applications to a plurality of gaming sites located in a plurality of regulatory regions via a wide area network. Each regulatory region has a regulatory scheme associated therewith. A plurality of gaming applications are stored on at least one central server. A subset of the gaming applications are distributed from the at least one central server to at least one of the gaming sites located in one of regulatory regions via the wide area network, the subset of gaming applications being determined according to the associated regulatory scheme.
Inventors:
Bartley K. Andre, Daniel J. Coster, Daniele De Iuliis, Richard P. Howarth, Steve Jobs, Jonathan P. Ive, Duncan Robert Kerr, Shin Nishibori, Matthew Dean Rohrbach, Douglas B. Satzger, Calvin Q. Seid, Christopher J. Stringer, Eugene Antony Whang, Rico Zörkendörfer
Abstract: Systems and methods for implementing an execution stack which stores frames for functions written in multiple programming languages are provided. The frames for functions written in different programming languages may be interleaved on the same execution stack. A data block on the execution stack may be utilized to traverse the execution stack around a frame by storing a stack pointer and frame pointer to a previous frame. Additionally, exceptions may be propagated, with conversion if necessary, through frames on the execution stack that are written in different programming languages.
Inventors:
Bartley K. Andre, Daniel J. Coster, Daniele De Iuliis, Richard P. Howarth, Jonathan P. Ive, Steve Jobs, Duncan Robert Kerr, Shin Nishibori, Matthew Dean Rohrbach, Douglas B. Satzger, Calvin Q. Seid, Christopher J. Stringer, Eugene Antony Whang, Rico Zorkendorfer
Inventors:
Bartley K. Andre, Daniel J. Coster, Daniel De Iuliis, Richard P. Howarth, Jonathan P. Ive, Steve Jobs, Duncan Robert Kerr, Shin Nishibori, Matthew Dean Rohrbach, Douglas B. Satzger, Calvin Q. Seid, Christopher J. Stringer, Eugene Antony Whang
Inventors:
Bartley K. Andre, Daniel J. Coster, Daniele De Iuliis, Richard P. Howarth, Jonathan P. Ive, Duncan Robert Kerr, Shin Nishibori, Matthew Dean Rohrbach, Douglas B. Satzger, Calvin Q. Seid, Christopher J. Stringer, Eugene Antony Whang
Inventors:
Bartley K. Andre, Daniel J. Coster, Daniele De Iuliis, Richard P. Howarth, Jonathan P. Ive, Steve Jobs, Duncan Robert Kerr, Shin Nishibori, Matthew Dean Rohrbach, Douglas B. Satzger, Calvin Q. Seid, Christopher J. Stringer, Eugene Antony Whang, Rico Zorkendorfer
Abstract: A video controller having a processor for processing executable instructions and associated data and a number of data ports, a method of acquiring extended display identification data (EDID) by a requesting one of the data ports is described. When on-board power supply is activated, an off-board power supply is deactivated and then the now active on-board power supply provides power to a memory device used to store the EDID and the executable instructions and associated data and to an on-board clock circuit capable of providing a high frequency clock signal. The on-board clock circuit, in turn, provides the high frequency clock signal from the on-board clock circuit to the memory device and if a memory read operation had been in progress when the on-board power supply was activated, then the memory read operation is completed.
Type:
Grant
Filed:
February 18, 2005
Date of Patent:
April 3, 2007
Assignee:
Genesis Microchip Inc.
Inventors:
Ali Noorbakhsh, David Keene, John Lattanzi, Ram Chilukuri