Abstract: An overlay mark for determining the relative position between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The overlay mark includes a plurality of working zones, which are used to calculate alignment between a first and a second layer of the substrate or between a first and a second pattern on a single layer of the substrate. Each of the working zones is positioned within the perimeter of the mark. Each of the working zones represents a different area of the mark. The working zones are configured to substantially fill the perimeter of the mark such that the combined area of the working zones is substantially equal to the total area of the mark.

Abstract: The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration.

Abstract: Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.

Abstract: Hardware, systems, devices, architecture and methods for a wagering game-specific platform features secure storage and verification of game code and/or other data. An external connection securely communicates with a computerized wagering gaming system. Some embodiments of the invention provide the ability to identify game program code as certified or approved. This is provided by use of various electronic devices and elements for encryption, including at least a device that is internally embedded in the gaming device that access digital signatures, encrypted files, encrypted compiled files and hash functions as well as other encryption methods. Such functions are able to be effected, and security and validation is advantageously applied to data loaded into storage media even while the gaming machine is in operation.

Abstract: Disclosed is a device and method for configuring a register in a PLD to operate as a logical AND gate. So configuring a register allows it to be used in a multiplication carried out by the PLD. A logic element includes a combinatorial logic section and at least one register interconnected with the combinatorial logic section. The register is configured to operate as a logical AND gate. The logic element can include a data input, a clear input, and a load input wherein the load input can be held high, a first bit to be ANDed can be input on the data input and a second bit to be ANDed can be input on the clear input. The logic element can, for example be configured to carry out at least a portion of a multiplication of a multiplicand and a multiplier.

Abstract: An overlay mark for determining the relative shift between two or more successive layers of a substrate via scanning is disclosed. The overlay mark includes at least one test pattern for determining the relative shift between a first and a second layer of the substrate in a first direction. The test pattern includes a first set of working zones and a second set of working zones. The first set of working zones are disposed on a first layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The second set of working zones are disposed on a second layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The first set of working zones are generally angled relative to the second set of working zones thus forming an “X” shaped test pattern.

Abstract: An image processing system to be mounted to a vehicle includes a radar adapted to measure distance and direction to an object based on reflected electromagnetic waves which are outputted to scan the exterior of the vehicle, an image-taking device such as a camera for obtaining an image, and an image processor for carrying out image processing on a specified image processing area in an image obtained by the image-taking device. The image processor is adapted to determine a center position of the image processing area according to a measurement point of an object detected by the radar and the size of the image processing area according to a beam profile of electromagnetic waves outputted from the radar.

Abstract: A hydrogen sensor includes a hydrogen-absorbing material, a thermoelectric element, an electrical circuit for driving the thermoelectric element, a thermometer for the hydrogen-absorbing material, a temperature control circuit for maintaining the hydrogen-absorbing material at a constant temperature using the thermoelectric element, a unit for calculating the exothermic value of the hydrogen-absorbing material based on the electrical current flowing from the drive circuit, and a unit for calculating the hydrogen uptake of the hydrogen-absorbing material based on the exothermic value.

Abstract: A method for process optimization to extend the utility of the HDP CVD gap fill technique modifies the characteristics of the HDP process (deposition and sputter components) in a dynamic mode in the course of filling a trench with dielectric material. As a result, the amount of dielectric deposited on the sidewall of the trench relative to that deposited at its bottom can be reduced and optimally minimized, thus improving the gap fill capability of the process. The dynamic modification of process characteristics provides enhanced process performance, since the optimization of these characteristics depends upon structure geometry, which is constantly changing during a gap fill operation. During the course of the gap fill operation, either at one or more discrete points or continuously, the evolution of the feature geometry is determined, either by direct measurement or in accordance with a growth model.

Abstract: Methods of preparing a low-k dielectric material on a substrate are provided. The methods involve using plasma techniques to remove porogen from a precursor layer comprising porogen and a dielectric matrix and to protect the dielectric matrix with a silanol capping agent, resulting in a low-k dielectric matrix. Porogen removal and silanol capping can occur concurrently or sequentially. If performed sequentially, silanol capping is performed without first exposing the dielectric matrix to moisture or ambient conditions.

Abstract: A macroscopic fluorescence illumination assembly is provided for use with an a imaging apparatus with a light-tight imaging compartment. The imaging apparatus includes an interior wall defining a view port extending into the imaging compartment to enable viewing of a specimen contained therein. The illumination assembly includes a specimen support surface sized and dimensioned for receipt in the imaging compartment, and oriented to face toward the view port of the imaging apparatus. The support surface is substantially opaque and defines a window portion that enables the passage of light there through. The window portion is selectively sized and dimensioned such that the specimen, when supported atop the support surface, can be positioned and seated over the window portion in a manner forming a light-tight seal substantially there between.

Abstract: Method and devices are provided for implementing high availability. Some implementations provide high availability for virtual switches of data networks. Each virtual switch acts as a single logical unit, while encompassing at least two physical chassis, referred to herein as a master chassis and a slave chassis. In some preferred embodiments, the active supervisor in the master chassis is configured as an active supervisor of the virtual switch and the active supervisor in the slave chassis is configured as the standby supervisor of the virtual switch.

Abstract: Methods and apparatus are described for creating, scheduling and delivering messages. A message having a first audio component is generated in response to input from a user. The input includes words entered by the user. The first audio component is operable to facilitate audible playback of the words. Delivery of the message at a future time to a communication device is scheduled in response to specification of the future time by the user. A connection to the communication device is established at the future time via a communications network. The message is transmitted over the connection such that the words associated with the first audio component of the message are audible via the communication device.

Abstract: When a voltage is applied between outside electrodes and a common electrode that constitute driving parts of a driving unit provided between a holder holding a lens and a lens barrel, as shown in FIG. 9, respective dielectric elastomers provided in the driving parts are slightly deformed in a direction that is crushed in an X1–X2 direction. Thus, the entire lens can be slightly moved in the direction of an arrow (X2-direction). This enables an optical axis O?—O? of the lens to coincide with or get closer to a reference optical axis.

Abstract: A direct current detection circuit has a zero-phase current transformer with source lines inserted therethrough for detecting current differences among them and generates a comparison voltage value based on a divided voltage value obtained between the zero-phase current transformer and a voltage divider resistor according to a change in the self-impedance of the zero-phase current transformer. An offset current is passed through the zero-phase current transformer to make it possible to detect on the basis of the comparison voltage value a direct current value in a range which is otherwise difficult to detect accurately on the basis of the comparison voltage value because of influence of hysteresis characteristic of the zero-phase current transformer. A control circuit detects a present direct current value based on the comparison voltage value and the value of the offset current.

Abstract: A transmission efficient packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed. The transmission efficient interface includes a bi-directional auxiliary channel arranged to transfer information between the multimedia source device and the multimedia sink device and vice versa, wherein the information transferred over the auxiliary channel includes a set of packet attributes. The interface also includes a unidirectional main link arranged to carry a number multimedia data packets from the transmitter unit to the receiver unit each having a multimedia data packet header. In the described embodiment, each of the headers is substantially reduced in size over what would otherwise be necessary since the packet attributes are communicated via the auxiliary channel prior to the transmission of the main link packets over main link thereby minimizing the packet overhead and providing a very high main link efficiency.