Abstract: Control panel function is provided to bus units coupled together by an I/O bus. At least one bus unit has the capability to issue control commands through the bus to one or more other bus units. A control facility is integrated into bus units, and makes full use of existing paths to processor registers and main storage. Control commands are distinguished from other bus communications, and executed by the control facility, to provide a full control panel function for each bus unit incorporating the control facility.

Abstract: A fully redundant safety interlock system is provided comprising, means for detecting the loss of light on a fiber optic link; controller means, coupled to said means for detecting, for determining the safety condition of the link based on the output of said means for detecting, and for controlling the radiant energy output of an optical transmitter, based on the determined safety condition, via redundant output control signals; and means, coupled to said controller means, responsive to said redundant control signals, for interconnecting the output of said controller means to transmitter drive circuitry to thereby adjust the radiant energy output by the transmitter. According to a preferred embodiment of the invention, the controller means includes an electronic implementation of two independent state machines, each of which redundantly determines the connection state of the optical link between two optical link cards.

Abstract: A method and apparatus are provided for uniquely identifying integrated circuit chips adapted for use with scan design systems and scan testing techniques. A predetermined identification number corresponding to each LSI chip to be identified is assigned. Each predetermined identification number has a predefined format. The assigned identification number is stored in a plurality of predefined shift register latches (SRLs) in the corresponding LSI chip to be identified. Then the LSI chip is identified by selectively reading out the stored predetermined identification number.

Abstract: Workstations are connected via workstation controllers to two computer systems where one of the workstation controllers is a primary or controlling workstation controller and the other workstation controller is connected to appear to the primary workstation controller as a workstation and is designated as the secondary or standby workstation controller. The standby workstation controller has its line impedance matching resistor connected to function as a line terminator but it can also function as a line driver resistor when the primary or controlling workstation controller fails, the failure of the primary or controlling workstation controller being detected by the secondary or standby workstation controller upon the failure of being polled by the primary or controlling workstation controller within a predetermined period of time. The line impedance matching resistor of the failing primary or controlling workstation controller then functions as a line terminator resistor.

Abstract: A data management mechanism for a processor system provides for management of data with minimum data transfer between processes executing work requests. Each process has storage areas for storing data associated with work requests. The data is described with descriptor elements in the work requests which indicate the location and length of segments of the data. Data is transferred to a process only if it is required for execution of a work request. Further work requests can be generated by a process executing a work request which reference the data without the process actually receiving the data. The segments of data may reside in storage areas of different processors with the descriptor elements of a work request defining a logical data stream.

Abstract: A lubricant film for a thin-film disk is disclosed. The lubricant film comprises a monolayer of fixed lubricant bonded to the surface of the thin-film disk and a mobile lubricant in contact with the layer of fixed lubricant. The monolayer of lubricant film is applied to the thin-film in a method comprising applying a lubricant composition to the surface of a thin-film disk, then heating the thin-film disk at a sufficient temperature for a sufficient time to bond or fix a portion of the lubricant composition to the disk; to evaporate a portion of the lubricant composition from the surface of the disk; and to dispose a portion of the lubricant composition as a mobile lubricant in contact with the fixed lubricant.

Abstract: A WORM data storage medium includes primary and secondary data storage areas in which data and pointers to allocated but unwritten update areas are written. Original and updated data is written in a write sequence or chain of primary data areas separated by branched secondary data storage areas. The most recent updated data is found in a two level search of primary and then secondary data storage areas in order to save time by searching only those secondary areas where the most recent update exist.

Abstract: An optical fiber link card communication module, and process for fabricating the module, where the module provides a parallel electrical interface to the user, facilitates high speed serial transmission of data over an optical data link, and contains a plurality of converters for performing conversions between both electrical and optical signals. The module further includes edge mounted optical components having leads mounted on the surface of a card (as opposed to standard pin-in-hole type leads) to minimize lead capacitance and inductance from the optical components to the card electronics, on board card control means for the converters and safety shut down means on the same card as the electrical and optical components.

Abstract: In a disk drive device having multiple disks on a spindle, one of the disks is written with a servo pattern prior to assembly of the servo disk with blank disks into the disk enclosure. The servo pattern consists of a first pattern arranged on each track center along one radial direction of the disk, and a second pattern arranged along the radial direction at each position corresponding to the position of each sector. Servo patterns on each of the disks, including the original servo disk are then written on each of the disks based on the original servo disk. If the disks, when assembled exhibit eccentricity, the second pattern will still be detected, permitting servo writing without complex equipment.

Abstract: The construction and display of operator messages representative of alert conditions in a network is described. Code points, which are strings of bits, are generated in response to an event in a device attached to the network. The code points are used to index predefined tables that contain relatively short units of text messages in operator selectable languages to be used in building an operator's information display. A product attached to a network, an alert sender, will generate a series of code points representative of desired display messages for an operator. The messages are indepedent of the specific alert sending product insofar as an alert receiver is concerned. The operator can also choose between detailed and general display messages. The code points are hierarchically arranged so that if the alert receiver does not have the most up to date set of messages, the alert receiver will display a more generic message which is still representative of the event.

Abstract: A real time data transformation and transmission apparatus transforms data from a first data device and transfers the transformed data to a second data device which need not have a data transfer rate consistent with the first data device. Data from the first data device is divided into blocks and is compressed by a compression device and written into a buffer. A controller controls the buffer to transmit compressed data to the second data device as a function of the data receiving rate of the second data medium provided that the buffer contains a predetermined amount of data. While the buffer is transmitting data, the compressor is compressing further blocks of data which are being written to the buffer such that the predetermined amount of data is stored in the buffer upon completion of the buffer transmitting a block of data. This ensures that complete blocks of data are transmitted to the second data medium at the data receiving rate of the second data medium.

Abstract: In a CSMA/CD communication protocol, data to be sent from one device on a communication network to another is put into frames, or predetermined sized pieces of information. One of the fields in a frame, the pad field, is used to make the total size of the frame large enough to ensure that a collision anywhere in the network with another frame is detected by the senders. The pad field is further used to identify when a data record will be continued in the next frame and also to identify when multiple data records are being sent in the same frame.

Abstract: An interprocess communication facility in a processor system provides for communication of data between at least two processes. The facility supports a plurality of different data transfer modes which are provided by storage management services of the processor or processors. A process interface provides a common interface for each communicating process to select data transfer modes independently of the data transfer mode chosen by the other communicating process. A data access control function is coupled to the process interface and to the storage management services. The data access control function controls the use of the storage management services as a function of the transfer modes chosen by the communicating processes. It is transparent to the processes as to which transfer mode was chosen by each other.

Abstract: A microcode branch, to one of a number of possible control words (sixteen control words are described), is based upon (1) the remaining operand length that is to be processed by a left to right instruction, and (2) by the byte alignment of the portion of the operand that currently resides in main storage interface registers. As a left to right instruction is being executed, the operand's new length and its new alignment, as they both will exist after a control word is executed, are determined. The new length and the new alignment are used to determine the addess of the next control word. A 16-way branch instruction has branch legs that are determined by the number of operand bytes that are left to be processed, and by the alignment of two operands in two storage registers that interface with main storage. This method and arrangement for microcode branching maximizes the amount of data that can be processed per processor cycle by the hardware upon execution of a left to right instruction.

Abstract: The flow of work requests in a server driven process to process communication environment is described. A mechanism is provided to facilitate work consistent with the server driven architecture when bus units do not have adequate DMA capabilities. Two ways of reversing control of transfer of work requests and data so that the server need not have master DMA capability are presented. Management of storage in a remote processor is used to transfer work and its associated data into storage accessible by a bus unit with slave DMA capability. The slave DMA bus unit then transfers the information into storage is manages. In another way of reversing the flow, a bus unit message is used to make the original server a requestor. The bus unit message contains information which varies the request sent by the requestor. In this manner, the server, which was the original requestor transfers information using its master DMA capability flow.

Abstract: Customized instructions for installation of a device having multiple variable components is described, and are generated by an instruction generator program. A device description file lists a desired set of components for the device. Each of the components is broken down into one or more installation tasks, and the tasks are sequenced in a desired order for installation of the device. Text and graphic modules for inclusion in the instructions are varied based on the physical characteristics of the components, and their interconnection. Scaled line drawings are also generated based on information about each component and its placement in the device.

Abstract: Storage addressing error detection circuitry detects addressing errors in a computer system during data transfers between an I/O unit and main storage where main storage has logical boundaries which if crossed can cause destruction of data. The central processing unit (CPU) of the computer system furnishes the I/O unit the starting address for the data transfer and thereafter the I/O unit furnishes addresses for completion of the data transfer. The starting address contains a hash value related to the logical boundaries. Each time the I/O unit presents an address with a hash value for a data transfer another hash value is generated from the remainder of the address passed by the I/O unit. If the two hash values do not compare equal, a logical boundary in main storage would be crossed and to prevent such an occurrence the storage operation is inhibited and an error signal is sent to the I/O unit which then terminates the data transfer.

Abstract: A data reading and modifying device of a computer system has a main storage for storing first data, portions of which are to be modified by various modifying data. The access speed of the main storage is slower than the speed at which the modifying data is accessed. A controller initiates fetches of first data from the main store and selects the modifying data. A register is coupled to the main storage for receiving and storing first data as it is provided from the main storage. Portions of the register are reserved for modifying data which is preferably inserted into the register before receipt of the first data as controlled by the controller. The first data received from the main storage is inserted into remaining portions of the register and insertion of, first data into portions reserved for modifying data is inhibited, such that modified data is available without a write back to the main storage location of the data to be modified.

Abstract: Storage serialization apparatus in a multiprocessor computer system enables multiple processors to concurrently execute instructions which access storage without materially affecting performance by keeping the amount of storage locked to a minimum, i.e., a page. The duration of serialization need be only for one instruction execution time and only instruction operands need be accommodated for serialization. Each storage request is intercepted by an associative register stack where there are two registers for each operand, one of the two being for operand page crossings. After a processor has locked access to an area of storage, execution of the instruction begins and all other processor are locked out but only with respect to that locked area. Other processors can access other storage areas during the instruction cycle. When the execution of the instruction completes, the processor releases the locked area of storage by invalidating the entries in its associative register array.

Abstract: An integrated semiconductor VLSI chip design that increases the number of driver circuits, or groups of driver circuits, that can be simultaneously switched. Timed driver gating signals, or driver enable signals, are used, in conjunction with physical grouping of driver circuits on the chip, to isolate switching drivers from quiet drivers. This construction and arrangement minimizes detrimental effects usually caused by noise that is generated when driver circuits switch.