Abstract: Apparatus for compressing and buffering large amounts of data, transferring the buffered data to a slower speed storage device and controlling the stopping and starting of the central processing unit (CPU) is provided for a virtual storage computer system where the data is collected in real time; the data being collected are all storage addresses to facilitate address tracing. Each real main storage address is collected to the external interface between the central processing unit (CPU) and main storage and converted to a virtual address. The virtual address is compressed and entered into a large buffer via buffer control logic. The buffer control logic sends a signal to stop the CPU when the buffer becomes full and restarts it at the exact point it had stopped after the buffer has been emptied by the transfer of data from it to a slower speed storage device.

Abstract: An I/O device control subsystem for controlling issuance of commands to one I/O device while it is doing I/O device to I/O device data transfers with another I/O device. The I/O device control subsystem has a timer for indicating current time. The time required to write the transferred data, known at the time the data transfer command is issued, is added to the current time. Then, when a command is issued to the first I/O device while the other I/O device is writing the transferred data, the time required for executing that command is determined as well as the time remaining for completion of the write operation and if the time required for execution of the new command is less than the remaining time, the new command is allowed to be executed.

Abstract: Extended control word decode circuitry increases the number of simultaneous functions performed during execution of a control word in the central processing unit (CPU) of a computer system. A first field of a control word is decoded into 2.sup.n decodes for testing or specifying a first set of CPU conditions. A second field in the control word is decoded into 2.sup.m -X decodes for testing or specifying a second set of CPU conditions. The X decodes, which together with the 2.sup.n decodes of the first field test or specify multiples or pairs of a third set of CPU conditions and inhibit the 2.sup.n decodes from testing or specifying said first set of CPU conditions.