Abstract: Two comparators are arranged to generate a pulse-width modulator (PWM) control pulse. The first comparator is arranged to start the PWM control pulse, while the second comparator is arranged to stop the PWM control pulse. The first comparator can be a high speed CMOS comparator that includes a built-in offset. The first and second comparators can be arranged such that the built-in offset of the first comparator dominates the overall operation at the start of the control pulse. The start of the PWM control pulse is initiated by a ramp voltage and a predetermined reference level instead of a clock edge. The PWM control pulse can be linearly varied down to a zero pulse width. The PWM control pulse may be used to control the on-time of the switching element in a switching-type converter.

Abstract: A differential voltage amplifier includes a dynamic level shifter circuit and an amplifier circuit. The dynamic level shifter circuit includes high-impedance current sources and resistors that are arranged to move the common-mode levels of a differential input signal to a signal level that is suitable for the amplifier circuit. The amplifier circuit may be single-ended or differential. The dynamic level shifter circuit may include one or more current sources that are arranged to provide improved performance for low common-mode levels. A dynamic biasing scheme may be employed to improve operation over varied common-mode ranges. A trimming circuit may be used to adjust offsets in the system. A DC chop arrangement may be employed to remove offsets in the system.

Abstract: A method and system is arranged to convert a differential low-voltage input signal (e.g. LVDS or RSDS) into a single-ended output signal. An operational trans-conductance amplifier (OTA) is configured to convert the input signal into a current. A trans-impedance stage is configured to convert the current into the single-ended output signal. The voltage associated with the output of the OTA corresponds to approximately VDD/2. The trans-impedance stage comprises an inverter circuit, a p-type transistor, and an n-type transistor. The transistors are arranged in a negative feedback configuration with the inverter. The single-ended output signal has a voltage swing that approximately corresponds to the sum of the VGS of the n-type transistor and the VGS of the p-type transistor. The output signal may be buffered by additional circuits such as an inverter, a Schmitt, as well as others.

Abstract: Optimization of a parameter can be achieved by a servo loop having a temperature sensor, a temperature change detector, and a parameter adjuster. The temperature sensor monitors the temperature of an electronic device while the parameter is varied. The temperature change detector detects whether the electronic device temperature is increasing or decreasing. The parameter has a value associated with minimum power consumption when the monitored temperature reaches a minimum. The parameter is adjusted dynamically to a new preferred value as operating conditions of the electronic device change.

Abstract: An oscillator circuit is coupled to an enable pin of an Voltage regulator so that total power consumption is minimized in the application. A filter capacitor is coupled to the Voltage regulator such that current is supplied to the load (the application) while the Voltage regulator is disabled. The frequency of the oscillator circuit is low such that power consumption by the oscillator is minimal. The duty cycle (DC) of the oscillator circuit is selected so that the output voltage across the load does not drop below minimum voltage requirements in the application. The total current (I) that is consumed by the system corresponds to: I=DC*Idq+(1−DC)*Iq+Iosc+Iapp, where Iq corresponds to the shutdown current of the LDO, Idq is the ground current of the LDO, Iosc is the oscillator operating current, and Iapp is the average current consumed by the application.

Abstract: The on-time of a pulse signal is controlled by comparing a ramp signal to an input signal that is dynamically selected from two signals. A first operating mode is active when a clock signal is in a first logic state, where the pulse signal is reset. A second operating mode is initiated when the clock signal changes from the first logic state to a second logic state. During the second operating mode, the ramp signal is compared to the first signal. A third operating mode is initiated when the ramp signal exceeds the first signal during the second operating mode. During the third operating mode, the pulse signal is set and the ramp signal is compared to the second signal. The pulse signal is reset when the when the ramp signal exceeds the second signal in the third operating mode such that the on-time of the pulse signal is controlled.

Abstract: A pulse frequency modulation switching regulator varies the forced off-time of a load circuit when the load circuit is subject to an overload or short circuit event. An on-switch of the circuit is deactivated for a variable time interval when an output current of the load circuit exceeds a threshold. The time interval that the on-switch is deactivated is dependent on an output voltage of the load circuit. The on-switch is deactivated for a short time interval when the load circuit is subject to a slight overload. The on-switch is deactivated for a long time interval when the load circuit is subject to a short circuit.

Abstract: A cascode stage is arranged to improve performance of an operational amplifier. The cascode stage includes transistors that are arranged to operate as a current mirror. Each side of the current mirror has a corresponding voltage at a corresponding node. One of the corresponding nodes corresponds to a high impedance node that is coupled to a subsequent stage of the amplifier. The voltages at the corresponding nodes are closely matched to one another such that the input referred offset in the amplifier is minimized and the power supply rejection ratio is improved (PSRR). A transistor threshold voltage and a transistor saturation voltage determine the headroom requirements of the cascode stage, such that low power supply voltage operation is possible. The biasing of the transistors in the cascode stage is simplified such that minimal biasing circuitry is required, and overall power consumption may be minimized.

Abstract: A clamp circuit stabilizes a battery charging system when a battery is detected as being decoupled from the system and a power supply is providing current to the system. A battery detect circuit detects when the battery is decoupled from the system. A biasing circuit provides a biasing current to the clamp circuit when the battery is detected as being decoupled from the system. The clamp circuit shunts current from a battery charge terminal to maintain a stable condition in the battery charging system such that the system can withstand constant charge from the power supply without becoming damaged. The clamp circuit is deactivated when the battery is coupled to the system. The battery detect circuit includes a power management circuit that limits the power dissipated by the system.

Abstract: Voltage regulators are exposed to extreme amounts of voltage over short periods of time during an electrostatic discharge (ESD) event. Shunt regulators require protection from ESD events. Capacitors are passive devices that allow current flow when not in a steady-state condition. An apparatus and method compensates for the extreme voltages inherent in ESD events. By providing capacitance across the gate-drain junction of the shunt device in combination with a gate resistor, a voltage can be applied to the gate of the active device upon commencement of an ESD event, and cause the active device to “turn on” The “turned on” active device provides a pathway for the excess voltage from the ESD event to follow and discharge so as to avoid catastrophic failures.

Abstract: Many modern CMOS processes are capable of drawing submicron gate lengths and can be used to produce lateral PNP transistors that have betas within a useful range. A bandgap voltage reference circuit is formed in a standard CMOS process and has lateral PNP transistors that are arranged to provide a &Dgr;VBE reference. A vertical PNP transistor is arranged to provide a VBE reference. The vertical PNP transistor can be relatively large, which reduces the effects of undesirable variances in manufacturing processes. The vertical PNP transistor can be relatively large because it does not affect the ratio of the lateral PNP transistors that are arranged to provide the &Dgr;VBE reference. The problem of offset voltages in the differential amplifier is made moot by applying the offset voltage, if any, to the &Dgr;VBE reference.

Abstract: A folded-cascode amplifier is arranged with a differential pair circuit, a current mirror circuit, and a cascode circuit. The differential pair is coupled to the current mirror circuit, while the cascode circuit is only coupled to one half of the current mirror circuit. A minimum number of transistors are employed such that overall speed is improved. An output stage with a compensation circuit may be coupled to an output of the cascode circuit. The cascode circuit is configured such that the compensation capacitor is driven with a current of approximately +/−2*I when slewing in the positive and negative directions.

Abstract: An improved vertical photo-detector cell is used in an imaging sensor. Sensor material associated with a given color in a vertical photo-detector cell is coupled to sensor material associated with the same color in an adjacent photo-detector cell such that photo-carriers from adjacent cells are combined. The coupled sensor materials result in an increased size sensor area for the given color. The increased sensor area associated with each pixel in the sensor results in increased sensitivity and improved fill factor for each color. In an imaging sensor array, the vertical photo-detector cells are arranged such that each color plane is arranged in a pattern. Each sensor in a pattern has a central portion and an extending portion. The central portion and the extending portion are each located about a geometrical center that is associated with a pixel in the array.

Abstract: A method and apparatus are arranged to provide a multi-bit digital signal that represents a normalized percentage of time that a signal is active. The apparatus includes an N-bit counter that is periodically reset to an initialization condition, and a logic block that processes the output of the N-bit counter. The N-bit counter is arranged to evaluate a monitored signal for each cycle of a clock signal, and modify the count accordingly. The logic block is configured to periodically scan the output of the N-bit counter after the expiration of a sampling time interval. The sampling time interval is determined by a timing circuit such as a window counter that is operated from the clock signal. The logic block periodically evaluates the output of the N-bit counter and provides the normalized multi-bit digital signal.

Abstract: A method and apparatus are arranged to provide an early comparison scheme for a pipelined ADC stage with a delay circuit. The pipelined ADC includes an amplifier that is biased by a precision bias circuit. The delay circuit includes inverting stages, where each inverting stage includes one or more current sources. The delay circuit is configured to provide a latch signal in response to a clocking signal for the pipelined ADC stage. The latch signal is utilized by one or more comparators for early evaluation of the output of the pipelined ADC stage. The current sources in the delay circuit may also be biased by the precision bias circuit such that variations in amplifier performance are tracked by variations in the performance of the delay circuit. Process, temperature, and power supply related variations in the timing may be minimized by the biasing arrangement of the amplifiers and the delay circuit.

Abstract: An LVDS circuit is biased by an output load resistor. The LVDS circuit is arranged to sense the current in the output load resistor, and provide additional biasing currents to the remaining circuitry. The LVDS circuit includes a driver circuit that has common-mode feedback to control the output common-mode levels by varying a resistance associated with a variable resistor. The current through the variable resistor is reflected to a pre-driver circuit that generates the drive signals for the driver using a local supply voltage that corresponds to the output high signal level (VOH). The current through the variable resistor is also reflected to a biasing circuit that generates the local supply voltage. The LVDS circuit can be implemented as an integrated circuit that has a reduced pin count using the self-biasing method.

Abstract: A high-speed charge-pump circuit includes an array of current source/sinks circuits that are selectable according to UP and DOWN control signals, and a programmable setting. Each current source/sink circuit includes a current source circuit and a current sink circuit. The current source and current sink circuits are coupled to cascode circuits to minimize charge feed-through at the output of the charge-pump circuit. Matched switching circuits are configured to absorb charges that are injected at a common node between the cascode circuits and the current source/sink circuits. A clamp adjustment circuit is arranged to provide clamp voltages to the common node when the current source/sink circuits are in an off mode such that switching speeds are improved. The reduced switching-times permit the charge-pump to operate at high speeds.

Abstract: An LDO regulator is arranged to provide regulation with a pass device, a cascode device, a level shifter, an error amplifier, and a tracking voltage divider. The error amplifier is arranged to sense the output voltage and provide an error signal to the pass device via the level shifter. The level shifter changes the DC level of the error signal such that the pass device is isolated from damaging voltages. The cascode device is arranged to increase the impedance between the output node and the pass transistor such that the LDO regulator can sustain input voltages that exceed process limits without damage. The cascode device is biased by the tracking voltage divider. The tracking voltage divider adjusts the biasing to the cascode device such that a decreased input voltages result in lower impedance, and increased input voltages result in higher impedance.

Abstract: A filtered reference voltage is provided with improved PSRR without the use of a large capacitor. First and second reference voltages are generated, where the reference voltages are centered about an input reference voltage. A first small valued capacitor circuit samples a selected one of the first and second reference voltages. The selected one is determined by the comparison between the filtered reference voltage and the input reference voltage. A second small valued capacitor circuit is periodically coupled to the first capacitor circuit such that charge redistribution occurs. The overall voltage on the second capacitor circuit is increased when the filtered reference voltage is less than the input reference voltage, or decreased when the filtered reference voltage is greater than the input reference voltage. The voltage from the second capacitor circuit is buffered to provide the filtered reference voltage. The overall system is suitable for an integrated circuit.

Abstract: A method and apparatus are directed to improving the response of a phase-locked loop (PLL) by reducing the jitter transfer characteristics. A new PLL system, referred to as an IS-PLL, includes an integrator and stability filter that are arranged to provide improved low frequency and high frequency performance while maintaining reduced jitter. The design of the IS-PLL is accomplished using superposition such that the integrator and stability filter designs are simplified. Design coefficients are chosen such that the system transfer function has a high frequency roll-off that is equivalent to a second order low-pass filter. Other design coefficients are chosen such that the system transfer function provides for improved DC tracking and reduced jitter when tracking peaks in an error signal. The IS-PLL has a third order system transfer function that can be realized with simplified design criteria.