Abstract: A method and apparatus is directed to a rail-to-rail MOS amplifier that operates with a very low power supply. An input stage amplifier operates over rail-to-rail common-mode voltages. The input stage amplifier includes two differential input stages that steer current to loads in a class AB turnaround stage. The class AB turnaround stage converts the differential signals into a single signal that is driven into an output stage amplifier. The output stage amplifier includes level shifting buffer amplifiers that are arranged to bias a pair of MOS output transistors. Each level shifting buffer amplifier is arranged to bias a MOS transistor in a sub-threshold operating region such that the MOS transistor operates as a resistor. The MOS resistor works in conjunction with a MOS diode to provide an AB bias voltage to a gate of a respective one of the output transistors.

Abstract: An apparatus for an improved output buffer includes a symmetrical pre-gain stage and a gain stage. The pre-gain stage includes a pair of matched differential amplifiers that are arranged to provide a differential intermediary signal. The gain stage is arranged to receive the differential intermediary signal and provide a single-ended output signal. The pre-gain stage differential amplifiers include transistors that are arranged as differential pairs, where each of differential pair transistors is minimally sized to provide very low capacitive loading. The pre-gain stage differential amplifiers are matched such that symmetrical amplification is obtained from the differential intermediary signal. The pre-gain stage arrangement provides for a differential intermediary signal such that common-mode noise rejection and power supply noise rejection are enhanced.

Abstract: An output driver includes an adjustable main output stage and a control circuit with a digital delay locked loop (digital DLL) circuit and an adjustable scaled output stage. The main output stage and the scaled output stage are both configured to adjust their strengths in response to a control signal generated by the control circuit. The control circuit receives a clock signal and propagates a transition through the scaled output stage. The DLL circuit compares the propagation time through the scaled output stage with a reference signal (that is dependent on the clock signal frequency) and generates the control signal as a function of comparison. The main output stage, receiving the same control signal, adjusts its strength in a corresponding manner.

Abstract: A method and apparatus is arranged to produce high precision output voltage matching in a multiple output power converter. A two-output voltage converter includes a positive and a negative voltage output that are approximately equal in magnitude. The power converter includes inductors, transfer capacitance circuitry, and a controlled switching circuit. In one operating mode, the switching circuit is closed, the inductors are charged, and energy from the input signal is stored in the transfer capacitance circuitry. In a second operating mode, the switching circuit is opened, and the stored energy is transferred to the output loads. The transfer capacitance circuitry is arranged to provide improved matching in the output voltages. The two-output power converter topology may be extended to provide multiple outputs.

Abstract: A power-off protection circuit for an LVDS line-driver eliminates initialization problems in a local LVDS driver circuit that are caused by a remote LVDS river when the local LVDS driver is disabled. The remote LVDS driver may introduce a signal into the substrate of the local LVDS driver when the local LVDS driver is in a power-off mode. A current source in the local LVDS driver couples power from a local power supply node to the local LVDS driver when power is active. A method and protection circuit connects the substrate of the current source to the local power supply when power is active, and decouples the substrate from the local power supply when power is deactivated. The remote LVDS driver cannot cause a false power supply signal in the local LVDS driver since the conduction path is disconnected. A first switching element couples a floating substrate node in the current source to the local power supply when the power is active.

Abstract: An electronic circuit generates a bias current that is proportional to a frequency of a reference clock signal in a switched capacitor circuit. The electronic circuit includes a capacitive circuit selectively coupled to a transistor supplied by a voltage reference circuit. During a first phase the capacitive circuit is charged by a current from the transistor, and during the second phase the capacitive circuit is discharged to ground. The duration of each phase is related to the reference clock signal. The average current corresponds to a bias signal and is filtered to reduce ripple in the bias signal before the bias signal is received by the switched capacitor circuit. The capacitive circuit is configured with a first and second capacitor arranged in a complimentary out-of-phase configuration. During a first phase, the first capacitor is charged and the second capacitor is discharged. During the second phase, the second capacitor is charged and the first capacitor is discharged.

Abstract: A start-up circuit for a bias generator circuit includes an oscillator, a power monitoring circuit and a controllable current source. As the power supplies begin to ramp up to their final voltage, the power monitoring circuit monitors power consumed by the oscillator. As the oscillator begins to ring, the power monitoring circuit couples a control signal to the controllable current source, which generates a current used to start-up the bias generator circuit. Once the bias generator circuit has achieved an active operating condition, the start-up circuit is disengaged from the bias circuit by disabling the oscillator. The start-up circuit does not consume any standby current when disabled, and does not effect the operation of the bias generator circuit.

Abstract: A differential input stage with full-rail sensing and reduced latch-up susceptibility includes an emitter-coupled pair, a current mirror, and several series resistors. For a NPN emitter-coupled pair, a series resistor is connected between the input node and the base of each transistor of the emitter-coupled pair, and a series resistor is connected between each load resistor and its corresponding current mirror transistor. The series resistors reduce current flowing into the PN junctions when power to the overall circuit is disabled but an input signal is present at the input terminals.

Abstract: A method and apparatus are provided for adjusting an offset in an electronic circuit by shifting at least one threshold voltage of a MOS transistor in an electronic circuit. By biasing a transistor into hard saturation, with sufficient supply voltage, charge carriers will be injected into the oxide layer of the MOS transistor over a predetermined time interval. Injection of charge carriers into the oxide layer of a MOS transistor causes the absolute value of the MOS transistor threshold voltage to increase. The injection of charge carriers is used to either intentionally increase or decrease the offset voltage in an electronic circuit due to mismatched components, process variations or to improve overall system accuracy or performance. In an operational amplifier or comparator, systematic offset voltage is measured at the output of the amplifier, and the threshold voltages of the differential input stage transistors are adjusted accordingly.

Abstract: An amplifier employs a first and second input stage amplifier, and an output stage amplifier for rail-to-rail operation. The rail-to-rail amplifier is driven by an input signal with a particular common-mode voltage. The first amplifier is active during a first range of common-mode voltages, while the second amplifier is active during a second range. A monitor circuit includes an input differential pair that operates at the same common-mode voltage as the first input differential pair in the first amplifier. The monitor circuit senses when the first amplifier has reached a condition where the amplifier begins to stop working by monitoring a current flowing in the input differential pair. The monitor circuit controls the bias current in the second amplifier's bias circuit such that the second amplifier is enabled when the current in the monitor circuit input differential pair drops down towards zero.

Abstract: A single cell voltage reference operates under low power supply requirements to provide a configurable voltage reference. The single cell voltage reference includes a diode device that is biased as a voltage source. Two series connected resistive devices are connected in parallel with the diode device. The diode is biased with a current that is proportional to delta Vbe/R, such that the impedance of the diode tracks R. Another current source that is also proportional to delta Vbe/R is provided at the junction of the two resistors such that the voltage across one of the two resistors may be employed as a reference voltage that is less than 1.2V. The ratio of the resistors and scales the reference voltage level. Voltages that are below 1.2V are provided that are temperature compensated similar to a band-gap reference. The diode voltage as driven by a current source determines the lower limit of the reference voltage.

Abstract: A differential output driver circuit produces a differential output signal in response to an input data signal. The differential output driver circuit provides for a controlled edge rate in the differential output signal when the input data signal changes logic states. Control signals are generated using an adjustable delay circuit, each subsequent control signal being delayed in time from the preceding control signal by a unit delay time. The control signals control N output drivers, each of the N output drivers having an output signal coupled to the differential output signal, and each contributing a portion of the differential output signal. When the input data signal changes from one logic state to another, the differential output signal will have a defined edge rate determined by the unit delay time and the contributing portion from each of the N output drivers. In one example, the unit delay time is determined by a delay time through a buffer that has a controlled current limit.