Abstract: A voltage reference circuit is arranged in a CMOS process based technology to provide a configurable voltage reference. The voltage reference includes bipolar transistors that are implemented as parasitic devices in the CMOS process. Two of the bipolar transistors are configured to generate a &Dgr;Vbe signal in the voltage reference circuit. An error amplifier cooperates with the two bipolar transistors via a control signal such that the control signal is related to &Dgr;Vbe/R. A first current source is coupled to another bipolar device, which is parallel connected to a resistor divider. The output of the resistor divider provides a divided reference signal that is related to the Vbe of the other bipolar device. Another resistor is coupled between a second current source and the output of the resistor divider such that an adjustable/temperature compensated reference signal is provided.

Abstract: A method and apparatus provide for accurate low current generation using switched capacitor techniques. The current generator includes a reference voltage generator that provides a reference signal to a switched capacitor integrator. In one example, the reference circuit includes a switched capacitor divider. The switched capacitor integrator circuit produces a voltage ramp in response to the reference signal and other timing signals. The rate of the voltage ramp is proportional to the ratio of capacitors in the switched capacitor integrator and a clock frequency that is associated with the timing signals. A feedback circuit impresses the voltage ramp across an output capacitor circuit that has a very low capacitance value. The capacitor is arranged to differentiate the voltage ramp to produce an accurate low current. The switched capacitor design is suitable for integration in a monolithic integrated circuit. The integrator and the feedback stage are periodically reset.

Abstract: A shunt regulator system includes protection to prevent a battery from overcharging. The system may be implemented in an integrated circuit. A control circuit is used to actuate one or more switches when one or more fault conditions are detected. The switches provide a conduction path to shunt current away from the battery such that the battery does not charge beyond a safe level. The control circuit may include a comparator that compares the battery voltage to a predetermined level, which may be adjusted based on various system requirements. A fault condition may result from defects and/or misuse, including: semiconductor processing defects such as a shorted resistor, manufacturing assembly defects such as improperly connected or defective components, utilizing a non-compliant charger, as well as others. The control circuit and the switches prevent the battery from being overcharged when one or more fault conditions occur.

Abstract: A display interface is arranged to processes analog input signals to provide digital output signals. The display interface includes a series of programmable current sources, an input buffer circuit, a first reference buffer circuit, a second reference buffer circuit, and an analog-to-digital converter. The programmable current sources are arranged to provide first and second reference signals, which are buffered by reference buffer circuits and provided to the analog-to-digital converter. The input buffer circuit provides a buffered input signal to the analog-to-digital converter, and operates in an open-loop configuration for improved operating speed. The analog-to-digital converter is configured to provide a digital output signal (DOUT) in response to the buffered input signal. The analog-to-digital converter includes gain and offset settings that are changed by adjusting the progranmnable current sources. The programmable current sources and reference buffer circuits are outside of the input signal path.

Abstract: The present invention provides for a virtual serial port (VSP) situated between a serial port in a mobile electronic device, applications that require a serial port connection handle, and other applications that require command-mode access to the serial port. Data-communication applications (e.g. web browsing, e-mail, etc.) connect to the serial port through the VSP. The VSP creates a virtual connection handle that is returned to the application. Command-mode requests (e.g., short messaging requests) are received by the hardware abstraction layer, translated into command-mode messages (e.g., AT commands) and placed in a queue. The VSP multiplexes the serial port between the currently-open data communication session (data-mode) and command-mode messages by periodically suspending the currently-open connection and processing one or more command-mode messages that are in the queue. A buffer continually stores incoming data while the data communication session is suspended.

Abstract: An auto-zeroed quantizer that has a unit delay characteristic employs switched capacitor techniques to adjust the input common-mode voltage to a proper common-mode voltage for the quantizer. A feed-forward auto-zero scheme is used to initialize the apparatus during an initialization phase. After the initialization phase, a differential input signal is amplified to provide a differential amplified signal. A positive feedback circuit is subsequently activated to increase the difference in the differential amplified signal until the difference saturates at a logic level. The logic level decision is stored in a memory circuit such as a latch. The unit delay quantizer may be utilized in a converter circuit such as a &Dgr;&Sgr; modulator.

Abstract: A method and apparatus provide for improved crowbar protection in a shunt regulator circuit including a shunt device. An over-temperature protection circuit may be combined with a fast-crowbar protection circuit such that maximum protection from damaging thermal energy is provided to a shunt device. The fast-crowbar protection circuit estimates the thermal energy in the shunt device based upon an integration method. By integrating a measured power over time the rise in temperature can be estimated such that the crowbar protection is enabled before the thermal energy can damage the shunt device. The integration method can be approximated using a piece-wise linear approximation such that the estimation circuitry can be simplified. A series of comparators and timing/delay circuits are employed to measure a current level in the shunt device over a given duration. The timing/delay circuits have memory such that heat build up and heat dissipation are modeled.

Abstract: A Sauer diode circuit is arranged to introduce a signal into a circuit to compensate for mismatch effects to various parameters in a current mirror circuit. Current matching between transistors is improved by providing matched errors such as forward current gain (Beta), early voltage, transconductance, channel-length modulation, as well as other sources of matching errors. The Sauer diode includes a series of transistors that are arranged to operate as a diode circuit that has errors that are matched to other components in an application circuit. Example application circuits include, but are not limited to reference circuits, operational amplifiers, comparators, analog-to-digital converters, digital-to-analog converters as well as other circuits that employ current mirror circuitry. The Sauer diode may be implemented in a single transistor technology such as MOS, BJT, FET, or a number of mixed technologies such as BiCMOS, BiFET and the like.

Abstract: A method and apparatus are directed to emulating an emitter follower with a small PNP transistor that is arranged in a PNP multiplier configuration. The PNP multiplier includes a PNP emitter follower and a current mirror. The PNP follower is coupled between the input and the output. A current mirror is coupled to the collector of the PNP follower such that mirror produces a current that is a scaled version of the collector current from the PNP follower. The current mirror is arranged to scale the PNP collector current by a factor of N. The effective output current from the PNP multiplier circuit corresponds to &bgr;·IIN·(N+1), where &bgr; corresponds to the large signal forward gain of the PNP follower. By multiplying the output current by a scaling factor, the effective forward gain of the PNP transistor is increased while utilizing a small geometry PNP device.

Abstract: An output stage for an operational amplifier includes a dynamically activated CMOS drive circuit that is arranged to improve the drive characteristics of the operational amplifier. The output stage includes bipolar transistors that are arranged to clamp the signal swing at an intermediary node in the operational amplifier. The bipolar transistors activate respective portions of the CMOS drive circuit based on the signal drive at the intermediary node. The CMOS driver circuit includes a p-type field effect transistor that sources additional current into the output signal when active, and an n-type field effect transistor that sinks additional current from the output terminal when active. The output stage may include additional circuitry to ensure that parasitic capacitances associated with the gates of the p-type field effect transistor and the n-type field effect transistors are discharged at appropriate times such that power consumption is reduced and high-speed operation is enhanced.

Abstract: A cascode stage includes a gain boost circuit arrangement in a folded cascode type of operational amplifier. The gain boost circuit arrangement improves the overall DC gain of the operational amplifier while maintaining good low noise performance with the resistive loads. The cascode stage includes a current mirror circuit, resistive loads, and a regulated (or gain boosted) cascode circuit. The resistive loads are arranged to minimize thermal noise, while the regulated cascode circuit is arranged to increase the output impedance of a current mirror The increased output impedance results in higher DC gain in the operational amplifier. The increased DC gain and low noise characteristics may be implemented in bipolar and FET technologies.

Abstract: An apparatus and method is related to a shunt regulator that includes two feedback control loops. The shunt regulator provides a charging current to a battery cell from a power source. The input voltage from the power source is limited by the first feedback control loop to ensure that the input voltage does not exceed the breakdown voltage of the shunt regulator. The output voltage from the shunt regulator is limited by the second feedback control loop to ensure that the output voltage does not exceed the maximum rated voltage of the battery. The dual feedback control loops provide maximum charging current to the battery, while protecting the shunt regulator and the battery from damage. The shunt regulator is suitable for implementation in an integrated circuit.

Abstract: A power management circuit for a battery operated electrical device that may include a number of switching circuits. The switching circuits are coupled between the battery and a corresponding one of various electronic sub-circuits. A battery monitoring circuit is arranged to monitor a voltage associated with the battery. Each switching circuit selectively couples a corresponding one of the electronic sub-circuits to the battery based on the battery voltage. In another example, the monitor circuit and the switching circuit functions are provided within the corresponding electronic sub-circuit. Battery power is conserved by selectively disabling (i.e., placing them in a sleep mode) the various electronic sub-circuits based on the battery voltage.

Abstract: A system and method is related to charger systems that require fault protection at an input terminal. A clamp circuit is activated when the power source is detected as disconnected from the system. The clamp circuit operates as a clamp that limits the input voltage by shunting current away from the input terminal. The clamp circuit operates as a standby protection circuit that may be part of shunt regulator and/or a crowbar system in a shunt regulator. The clamp circuit prevents an “in-rush” of current from creating a dangerous condition in a charging device (i.e., battery operated) when the power source is initially engaged. The clamp circuit is deactivated when the detected power supply voltage is above a battery voltage of the device.

Abstract: A linear regulator includes an amplifier that provides a control signal in response to a comparison between a feedback signal and an output signal. A pass element in the regulator selectively couples power from an unregulated power signal to an output node in response to the control signal. A compensation circuit that includes negative gain is arranged to provide the feedback signal in response to an output signal at the output node. In one example, the compensation circuit includes an inverting amplifier that provides an intermediary signal in response to the output signal, and the intermediary signal is coupled to a feedback network that provides the feedback signal. In another example, the compensation circuit includes an inverting amplifier that cooperates with a feedback network to provide the feedback signal. The closed-loop transfer functions of the compensation circuits provide a feed-forward zero that enables stable operation of the LDO regulator.

Abstract: A segmented digital-to-analog converter circuit employs a tri-level technique to provide an output current in response to a bit code. DAC slice circuits are activated in unary fashion in response to their respective control signal, which are provided by a decoder circuit in response to the high-order bits. Each DAC slice circuit provides a binary weighted current to a summing node in response to the middle-order bits. One of the DAC slice circuits is selected to direct a portion of its total current to the input of a DAC_LOW circuit, where the input current is divided to provide a divided current to the summing node in response to the low-order bits. At certain code transitions a different DAC slice circuit is selected to provide the input current, and the previously selected DAC slice circuit redirects its total current to the summing node such that differential non-linearity errors are minimized.

Abstract: A method and apparatus is directed to generating an improved temperature coefficient for the current limit in a switching regulator/driver circuit. The current limit sense circuit includes a comparator that compares two signals to determine when the current limit has been exceeded. One signal is produced from a temperature independent voltage source, a trans-conductance cell, and a sensor resistor circuit. Another signal is produced by an active output circuit, such that the signal corresponds to the current associated with the switching regulator/driver circuit. The current sensed by the regulator/driver is temperature dependent due to the resistances in the active output circuit, the sensor resistor circuit, and the trans-conductance cell. Each of these resistances has a temperature coefficient. The temperature coefficients determine the amount of temperature dependence in the sensed switching/regulator current.

Abstract: Apparatus and method that provide for a Buck regulator with reduced open-switch voltage requirements. The buck regulator includes a transformer with a primary coil that is charged by an input voltage when the semiconductor switching circuit is in a closed circuit condition. A secondary coil of the transformer is arranged to provide an auxiliary regulated potential that may be coupled to an auxiliary load. The auxiliary regulated potential is further arranged to operate as a virtual ground node with respect to the semiconductor switching circuit such that the open circuit voltage requirements for the semiconductor switching circuit are reduced. The open circuit voltage across the semiconductor switching circuit is approximately equal to the input voltage minus the voltage of the virtual ground node.

Abstract: A power-on sense circuit accurately senses a power-on condition when a power supply voltage exceeds a desired trigger voltage level. The power-on sense circuit includes a voltage-to-current converter circuit and a beta-multiplier reference circuit. The voltage-to-current converter circuit and the beta-multiplier reference circuit generate currents that relate to the power supply voltage. By sensing a balanced current operating condition with the beta-multiplier reference circuit, the power-on sense circuit determines when a desired trigger voltage has been achieved. The trigger voltage level has a zero temperature coefficient at median operating temperatures, and has a slightly downward curvature shape without the need for high-current resistor-dividers or bandgap circuits. The power-on sense circuit may be adapted for use as a power-on reset signal. By adding an amplifier stage to the outputs signal, the power-on sense circuit may also be used as an analog reference voltage generator.

Abstract: An apparatus and method for an improved integrator provides for a regulated common-mode voltage. The improved integrator is arranged as a switched capacitor circuit that includes a differential amplifier. The common-mode input voltage of the differential amplifier is regulated by proper arrangement of the switched capacitor circuit. By regulating the common-mode input voltage, the performance of the differential amplifier is improved. Since the common-mode input voltage is regulated, it is possible to operate the improved integrator at power supply levels below 2V. The improved integrator operates with three single-ended reference signals such that the integrator design is simplified and overall costs are reduced. Capacitor ratios may be adjusted to scale the input common-mode voltage of the differential amplifier. The improved integrator may be arranged as a delayed integrator or a non-delayed integrator by changing the control signals on the switches.