Patents Represented by Attorney Brian A. Carlson
  • Patent number: 5959298
    Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A shallow etch stop trench (46) is first ion milled around each ceramic island on front side and then filled with an etch stop material (e.g. parylene 48). An optical coat (e.g transparent metal layer 54, transparent organic layer 56 and conductive metallic layer 58) is elevated above the etch stop material by an elevation layer (e.g. polyimide 49). For some applications, it has been experimentally verified that there is no loss, and sometimes a measured increase, in optical efficiency when the optical coating is not planar in topology. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 86) containing a massive array of sensing circuits.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: September 28, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Robert A. Owen
  • Patent number: 5912486
    Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: June 15, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5851896
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti--Al--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 22, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5847390
    Abstract: A focal plane array (30) for a thermal imaging system (20). The focal plane array (30) may include a number of thermal sensitive elements (42) bounded by a border (41). The thermal sensors (40) may provide a sensor signal output representative of the thermal radiation incident to the focal plane array (30). A multi-layer common electrode (36) may be coupled to the thermal sensitive elements (42) and the border (41). An optical coating (34) sensitive to infrared radiation may be provided in communication with the common electrode (36).
    Type: Grant
    Filed: April 9, 1997
    Date of Patent: December 8, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: John P. Long, Donald A. Rogowski
  • Patent number: 5825055
    Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelectric oxide) on the germanium layer. Preferably, the germanium layer is epitaxially grown on the semiconductor substrate. This is also a semiconductor structure, comprising: a semiconductor substrate; a germanium layer on the semiconductor substrate; and a high-dielectric constant oxide on the germanium layer. Preferably the germanium layer is single-crystal. Preferably the substrate is silicon and the germanium layer is less than about 1 nm thick or the substrate is gallium arsenide (in which case the thickness of the germanium layer is not as important). A second germanium layer 40 may be grown on top of the high-dielectric constant oxide and a conducting layer 42 (possibly epitaxial) grown on the second germanium layer.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: October 20, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5792377
    Abstract: An array of thermal sensitive elements (16) may be formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of electrically conductive contacts (60) is formed to define in part masked (61) and unmasked (68) regions of the substrate (46). A second layer of electrically conductive contacts (62) may be formed on the first layer of contacts (60). A mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). The unmasked regions (68) are exposed to an etchant (70) and irradiated to substantially increase the reactivity between the unmasked regions (68) and the etchant (70) such that during irradiation, the etchant (70) removes the unmasked regions (68) substantially faster than the first layer of contacts (60) and the mask layer (66).
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: August 11, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan, Scott R. Summerfelt
  • Patent number: 5793057
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an amorphous nitride barrier layer (e.g. Ti--Si--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the amorphous nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The amorphous nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 11, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5781404
    Abstract: A preferred embodiment of this invention comprises a first thin dielectric buffer layer of a first leakage-current-density material (e.g. strontium titanate 32) with a first moderate-dielectric-constant, a high-dielectric-constant layer of a second leakage-current-density material (e.g. barium strontium titanate 34) overlaying the first thin dielectric buffer layer, and a second thin dielectric buffer layer of a third leakage-current-density material (e.g. strontium titanate 36) with a second moderate-dielectric-constant overlaying the high-dielectric-constant layer, wherein the first and third leakage-current-density materials have substantially lower leakage-current-densities than the second leakage-current-density material. The first and second thin moderate-dielectric-constant buffer layers (e.g. strontium titanate 32, 36) substantially limit the leakage-current-density of the structure, with only modest degradation of the dielectric constant of the structure.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 14, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Howard Roy Beratan
  • Patent number: 5746930
    Abstract: An array of thermal sensitive elements (16) may be formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of electrically conductive contacts (60) is formed to define in part masked (61) and unmasked (68) regions of the substrate (46). A second layer of electrically conductive contacts (62) may be formed on the first layer of contacts (60). A mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). The unmasked regions (68) are exposed to an etchant (70) and irradiated to substantially increase the reactivity between the unmasked regions (68) and the etchant (70) such that during irradiation, the etchant (70) removes the unmasked regions (68) substantially faster than the first layer of contacts (60) and the mask layer (66).
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: May 5, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan, Scott R. Summerfelt
  • Patent number: 5737818
    Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 and contact vias 23 in a substrate 20; depositing a bias contact metal 32 into the vias 23 forming biasing contact areas around a periphery of the substrate 20; depositing a first trench filler 24 in the trenches 22 and vias 23; replanarizing; depositing a common electrode layer 25 over the thermal isolation trenches and the biasing contact areas; mechanically thinning the substrate 20 to expose the biasing contact area 32 and the trench filler 24; depositing a contact metal 34 on the backside of the substrate 20, the exposed trench filler 24 and the exposed bias contact area; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. The thermal isolation trenches 22 and the bias contact vias 23 may be formed by ion milling or laser vaporization.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: April 14, 1998
    Assignee: Texas Instrument Incorporated
    Inventors: Steven N. Frank, James F. Belcher, Charles E. Stanford, Robert A. Owen, Robert J. S. Kyle
  • Patent number: 5729054
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 17, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa
  • Patent number: 5708303
    Abstract: This is a device and method of optimizing capacitance and performance for multilevel interconnects. The device comprising: a semiconductor layer 70; a first high-k layer 68 above the semiconductor layer; a first insulating layer 66 above the first high-k layer 68; an interconnect layer 58 above the first insulating layer 66; a second insulating layer 64 around the interconnect layer 58; and a second high-k layer 52 above the second insulating layer 64 and the interconnect layer 58. The device may have a low-k material inserted between closely spaced metal interconnects. Alternatively, the device may have air gaps between closely spaced metal interconnects. In addition, the first high-k layer may be used as an oxide etch stop.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: January 13, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Shin-Puu Jeng
  • Patent number: 5696018
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 9, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa
  • Patent number: 5679267
    Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A shallow etch stop trench (46) is first ion milled around each ceramic island on the front side and then filled with an etch step material (e.g. parylene 48). An optical coat (e.g transparent metal layer 54, transparent organic layer 56 and conductive metallic layer 58) is elevated above the etch step material by an elevation layer (e.g. polyimide 49). For some applications, it has been experimentally verified that there is no loss, and sometimes a measured increase, in optical efficiency when the optical coating is not planar in topology. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 86) containing a massive array of sensing circuits.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: October 21, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Robert A. Owen
  • Patent number: 5665628
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an amorphous nitride barrier layer (e.g. Ti--Si--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the amorphous nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The amorphous nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 9, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5656852
    Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to fore a top surface with rounded comers on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
  • Patent number: 5653892
    Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A front side optical coating (e.g. transparent metal layer 44, transparent organic layer 46 and conductive metallic layer 48) is elevated above the substrate between the ceramic islands. This allows additional material (e.g. polyimide 38) between the optical coating and the substrate above the regions where cavities are to be etched. Etching of the cavities (72) is performed from the back side of the substrate without damaging the front side optical coating. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 80) containing a massive array of sensing circuits.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: August 5, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Robert A. Owen
  • Patent number: 5653851
    Abstract: A method to anisotropically etch a titanate wafer (16 or 39) is provided. The method includes the steps of generating a plasma (32) and mixing an organic acid reagent with the plasma (32). The titanate wafer (16 or 39) is then exposed to the plasma (32) and organic acid reagent mixture thereby etching (42) the titanate wafer (16 or 39).
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: August 5, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Gail D. Shelton
  • Patent number: 5652150
    Abstract: A preferred embodiment of this invention is a hybrid semiconductor imaging structure comprising a high speed signal conditioning substrate (e.g. Si 12) and an imaging substrate (e.g. HgCdTe 10) mounted on the conditioning substrate using an adhesive layer (e.g. epoxy 31). Infrared-sensitive time delay and integration CCD columns (14) charge coupled to sense nodes (e.g. diodes 16) are disposed in the imaging substrate. High speed signal processing channels (e.g. capacitive transimpedance amplifier 18, correlated double sampling circuit 20 and multiplexing shift register 22) are disposed in the conditioning substrate. The sense nodes are connected to the signal processing channels with low capacitance hybrid leads (e.g. Al 17).
    Type: Grant
    Filed: March 12, 1996
    Date of Patent: July 29, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Mark Vogel Wadsworth, Sebastian Ronald Borrello, Roland Wilby Gooch
  • Patent number: 5650646
    Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: July 22, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt