Abstract: An improved method of forming a capacitor electrode for a microelectronic structure such as a dynamic read only memory is disclosed which has a high dielectric constant (HDC) material as a capacitor dielectric. According to an embodiment of the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material.

Abstract: A preferred embodiment of this invention is a silicon-on-insulator structure comprising a semiconductor substrate (e.g. Si 36), a buried insulator layer (e.g. SiO.sub.2 34) overlaying the substrate, wherein the buried layer is buried at two or more predetermined depths, and a surface silicon layer (e.g Si 32) overlaying the buried insulator, wherein the surface silicon layer has two or more predetermined thicknesses. Generally, by patterning and etching a screening material (e.g. SiO.sub.2 30) prior to ion implantation, preselected areas of the substrate with less or no screen material are formed with a thicker surface silicon layer, while other areas with more screen material are formed with a thinner surface silicon layer. The areas of different surface silicon thickness can be used to implement devices with different characteristics based on those thicknesses, within the same integrated circuit.

Abstract: A preferred embodiment of this invention is a hybrid semiconductor imaging structure comprising a high speed signal conditioning substrate (e.g. Si 12) and an imaging substrate (e.g. HgCdTe 10) mounted on the conditioning substrate using an adhesive layer (e.g. epoxy 31). Infrared-sensitive time delay and integration CCD columns (14) charge coupled to sense nodes (e.g. diodes 16) are disposed in the imaging substrate. High speed signal processing channels (e.g. capacitive transimpedance amplifier 18, congelated double sampling circuit 20 and multiplexing shift register 22) are disposed in the conditioning substrate. The sense nodes are connected to the signal processing channels with low capacitance hybrid leads (e.g AI 17).

Abstract: A thermal imaging system (10) including a housing (12) having a cavity (28) therein is provided. A plurality of thermal sensors (14) are placed in the cavity (28) of the housing and an IR window (16) in the opening of the cavity protects the thermal sensors (14). The IR window (16) includes first (18) and second (20) faceplates formed from an IR transmissive material and a honeycomb support structure (22) between the faceplates for supporting the faceplates. The window (16) may also include an adhesive layer (25 & 26) between each faceplate and the support structure (22) for adhering each faceplate to the support structure (22).

Abstract: A thermal imaging system (10) contains a focal plane array (30) including a plurality of thermal sensors (32) mounted on a substrate (62). Each thermal sensor (32) includes a film layer (34) of infrared sensitive material which is both electronically and thermally isolated from the associated integrated circuit substrate (62). An image may be formed on the film layer (34) in response to infrared radiation from a scene (12). Electromagnetic radiation (22) from a source (visible light or near infrared) (20) is used to reproduce or transfer the image from the thermal sensors (32) onto the first surface (68) of the substrate (62). A thermoelectric cooler/heater (66) may be provided to optimally adjust the temperature of the substrate (62) to improve overall image quality.

Abstract: A thermal imaging system (10) contains a focal plane array (14) including a plurality of thermal sensors (50) mounted on a substrate (52). The focal plane array (14) generates both a reference signal which represents the temperature of the substrate (52) and a biased signal corresponding to the total radiance emitted by a scene (11). Electronics (16) process the reference signal and the biased signal to obtain an unbiased signal representing radiance differences emitted by objects in the scene (11). A thermoelectric cooler/heater (38) may be provided to optimally adjust the temperature of the substrate (52) to improve overall image quality. Each thermal sensor (50) contains an electrode (66 and 68) that electrically couples the thermal sensor (50) to the substrate (52) and also allows the thermal sensor (50) to deflect, contact, and thermally shunt with the substrate (52).

Abstract: An inverted thin film resistor structure comprises a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads (e.g. Al 36) overlaying a supporting layer (e.g. SiO.sub.2 32), an interlevel dielectric layer (e.g. SiO.sub.2 40) overlaying the supporting layer, and planarized so as to expose a top contact portion of the metallic interconnect leads, and an inverted thin film resistor (e.g. TaN 44) overlaying a portion of the planarized interlevel dielectric layer and overlaying the exposed top contact portions of the metallic interconnect leads. The novel inverted thin film resistor structure does not require a protective metal layer and does not require any vias in direct contact with the resistor. In addition, both the thin film resistor and the metallic interconnect can be formed with pattern and etch techniques.

Abstract: A mesa-type structure (52) is formed from polyimide (or a similar polymer material) to achieve a supporting structure for mounting a focal plane array (30 and 130) on an integrated circuit substrate (70 and 170). In an exemplary thermal imaging system (20 and 120), a thermal isolation structure (50 and 150) is disposed on an integrated circuit substrate (70 and 170) for electrically connecting and mechanically bonding a corresponding focal plane array (30 and 130) of thermal sensors (40 and 140). Each mesa-type structure (52 and 152) initially includes a polyimide mesa (54) over which is formed a reinforcing layer (56 and 156) and a metal conductor (58, 158 and 168) that extends from the top of the mesa-type structure (52 and 152) to an adjacent contact pad (72, 172 and 174). After the focal plane array (30 and 130) is bonded to the corresponding array of mesa-type structures (52 and 152), the polyimide mesas (54) are removed to create void spaces (60 and 160).

Abstract: A novel method etching through a substrate (e.g. BST 22) comprises removi A n5 Vthick substrate material from the backside of the substrate to form vias (e.g. cavity 24) all the way to the back surface of a frontside thin film (e.g. optical coating 20). To prevent damage to the frontside thin film while etching from the backside of the supporting substrate, the periphery of each frontside pixel is surrounded by a trench (e.g. etch stop trench 30) much deeper than the thickness of the thin film but also significantly shallower than the thickness of the substrate. This trench is then filled with an etch stop material (e.g. photoresist 32). This etch stop may be partially removed by the backside etching method but provides a tolerant means of recognizing when to stop etching before frontside film damage occurs. After etching the substrate down to and partially through the etch stop, the assembly is removed from the substrate etching medium.

Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 20) which are fabricated from novel materials using unique methods of patterning. Trenches (22) are formed in the ceramic substrate from the front side and filled with a filler material (e.g. parylene 24). An elevation layer (e.g. polyimide 26) is deposited above the filler material, and a front side optical coating (e.g. transparent metal layer 34, transparent organic layer 36 and conductive metallic layer 38 ) is elevated above the substrate between the ceramic islands. The elevation layer provides added protection to the optical coating during filler material removal. The substrate is thinned from the back side down through a portion of the trench filler material. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 62) containing a massive array of sensing circuits.

Abstract: A bonding apparatus (40) is provided for use in coupling a first substrate (20) with flip chip type interconnections (24) to a second substrate (22) having matching flip chip type interconnections (26). The bonding apparatus (40) includes a pedestal assembly (50) which may be used to align and couple the first substrate (20) with the second substrate (22) and transport the substrates (20 and 22) from the bonding apparatus (40) to a heater assembly (110). Magnetic force is used to maintain the alignment of the first substrate (20) with the second substrate (22) during temperature cycling within the heater assembly. The pedestal assembly (50) includes a magnet slidably disposed on the exterior of the pedestal assembly (50). For some applications, the magnet (60) may be formed from one or more permanent magnets. For other applications, magnet (60) may be formed from one or more electromagnets.

Abstract: An adhesive ohmic contact made to a p-type semiconductor metal substrate or layer (10) comprises tin. The contact preferably includes a tin film (24) approximately 2000 .ANG. in thickness. The p-type semiconductor compound contains mercury and, while described in conjunction with Hg.sub.1-x Cd.sub.x Te, other elements exhibiting group II and group VI chemical behavior and properties may be used. A cap layer (30) is deposited over film (24), followed by insulating layer 32. Via (34) is then formed and, to complete contact (50), a metal (36) is deposited inside via (34).

Abstract: A hybrid semiconductor imaging structure comprising a high speed signal conditioning substrate (e.g. Si 12) and an imaging substrate (e.g. HgCdTe 10) mounted on the conditioning substrate using an adhesive layer (e.g. epoxy 31). Infrared-sensitive time delay and integration CCD columns (14) charge coupled to sense nodes (e.g. diodes 16) are disposed in the imaging substrate. High speed signal processing channels (e.g. capacitive transimpedance amplifier 18, correlated double sampling circuit 20 and multiplexing shift register 22) are disposed in the conditioning substrate. The sense nodes are connected to the signal processing channels with low capacitance hybrid leads (e.g A1 17).

Abstract: In an exemplary thermal imaging system (20, 120, 220 and 320), a thermal isolation structure (50 and 150) is disposed on an integrated circuit substrate (70 and 170) for electrically connecting and mechanically bonding a focal plane array (30 and 230) of thermal sensors (40 and 240). Each mesa-type structure (52, 54 and 152) includes at least one mesa conductor (56, 58, 156 and 158) that extends from the top of the mesa-type structure (52, 54 and 152) to an adjacent contact pad (72 and 74). The mesa conductors (56, 58, 156 and 158) provide both biasing voltage (V.sub.B) for the respective thermal sensor (40 and 240) and a signal flow path (V.sub.S) for the respective thermal sensor (40 and 240). The mesa conductors (56, 56, 156 and 158) may be used to provide biasing voltage (V.sub.B) to either a single ferroelectric element (242) or a pair of ferroelectric elements (42 and 44).

Abstract: An improved pyroelectric material comprises a polycrystalline material doped with at least one donor element such that the polycrystalline material has a grain size less than 10 .mu.m (or 5 .mu.m) and a Figure of Merit greater than 90 nC/(cm.sup.2* K). In the preferred embodiments the polycrystalline material is barium strontium titanate or calcium-substituted barium strontium titanate. The donor element may be Nb, Ta, Bi, Sb, Y, La, Ce, Pr, Nd, Sm, Gd, Tb, Dy, Ho, Er or a combination thereof. The material may additionally be doped with an accepter such as Co, Cu, Fe, Mn, Ru, Al, Ga, Mg, Sc, K, Na, U, In, Mg, Ni, Yb or a combination thereof to control the resistivity. Other structures and methods are also disclosed.

Abstract: A silicon on insulator integrated circuit device is provided which comprises a substrate (10), a buried oxide layer (12), and an outer silicon layer (14). A buried (p)-layer (16) and a buried (n)-well region (26) are formed in order to position (p)-(n) junctions beneath (n)-channel and (p)-channel devices respectively formed in the outer silicon layer (14) outwardly from the (p)-layer (16) and (n)-well (26).

Abstract: A thermal detection system (10, 110, 210) includes a focal plane array (20, 120, 220), a thermal isolation structure (40, 140, 240), and an integrated circuit substrate (60, 160, 260). The focal plane array (20, 120, 220) includes a plurality of thermal sensors (30, 130, 230). The thermal isolation structure (40, 140, 240) includes mesa-type formations (44, 146, 148, 244) and bridge structures (42, 142, 144, 242) that provide thermal isolation, signal transport, and structural support of the focal plane array (20, 120, 220) when mounted on the integrated circuit substrate (60, 160, 260). Thermal detection system (10) includes an infrared absorber and common electrode assembly (22) which provides a bias voltage to all thermal sensors (30). Thermal detection system (110) has a plurality of electrically isolated thermal sensors (130), each thermal sensor (130) is supported by bridge structures (142, 144), which provide a bias voltage to and receive a signal voltage from the thermal sensor (130).

Abstract: In an exemplary thermal imaging system (20, 120, 220 and 320), a thermal isolation structure (50 and 150) is disposed on an integrated circuit substrate (70 and 170) for electrically connecting and mechanically bonding a corresponding focal plane array (30, 130, and 230) of thermal sensors (40, 140, and 240). Each mesa-type structure (52, 54 and 152) includes at least one mesa conductor (56, 58, 156 and 158) that extends from the top of the mesa-type structure (52, 54 and 152) to an adjacent contact pad (72 and 74). The mesa conductors (56, 58, 156 and 158) provide both biasing voltage (V.sub.B) for the respective thermal sensor (40 and 240) and a signal flowpath (V.sub.s) for the respective thermal sensor (40 and 240). The mesa conductors (56, 58, 156 and 158) may be used to provide biasing voltage (V.sub.B) to either a single ferroelectric element (242 and 243) having a void space (277 and 279) or a pair of ferroelectric elements (42 and 44).

Abstract: A thermal detection system (100, 200) includes a focal plane array (102, 202), a thermal isolation structure (104, 204) and an integrated circuit substrate (106, 206). The focal plane array (102, 202) includes thermal sensors (114, 214) formed from a pyroelectric element (116, 216), such as barium strontium titanate (BST). One side of the pyroelectric element (116, 216) is coupled to a contact pad (110, 210) disposed on the integrated circuit substrate (106, 206) through a mesa strip conductor (112, 212) of the thermal isolation structure (104, 204). The other side of the pyroelectric element (116, 216) is coupled to a common electrode (120, 220). In one embodiment, slots (128) are formed in the common electrode (120) intermediate the thermal sensors (114) to improve inter-pixel thermal isolation. In another embodiment, slots (236) are formed in the optical coating (224) to improve inter-pixel thermal isolation.

Abstract: A method is provided for reducing leakage current in an integrated circuit (24). A first doped region (18) having a first conductivity type is formed in a semiconductor layer (10) having a second conductivity type, such that a second doped region (20) having the first conductivity type is formed in the semiconductor layer (10). The second doped region (20) is less conductive than the first doped region (18). The first doped region (18) is removed from the semiconductor layer (10), such that the second doped region (20) substantially remains in the semiconductor layer (10). The integrated circuit (24) is formed to include the second doped region (20) and the semiconductor layer (10).