Abstract: The electronic circuit contains dual edge triggered flip-flop, which loads data on both the rising edge and the falling edge of a clock signal. The clock signal is supplied by a clock supply circuit with an enable input and a source input for receiving a source signal. The clock supply circuit toggles the clock signal as from an earliest available edge of the source signal after the enable signal at the enable input switches to an active state, irrespective of a polarity of said earliest available edge.

Abstract: An RF mixer utilizing frequency and bias compensation for improved performance characteristics. The RF mixer receives bias signals that are dependent on V.sub.CC levels to internally balance the local oscillation received and mix the perfectly bias balanced internally generated oscillation signal with the RF input.

Abstract: An approach for demodulating a frequency-modulated signal involves processing a frequency-modulated signal with a phase shifter network to provide a demodulated signal that has a relatively constant amplitude around the center frequency of the frequency-modulated signal and that exhibits a relatively linear phase change over an operational frequency range. Embodiments of the invention include a phase shifter network, using N number of cascaded all-pass filters, that receives as an input a limited amplitude signal and outputs a phase-shifted limited amplitude signal that is mixed with the limited amplitude signal. The phase shifter network may also comprise a low-pass bessel filter.

Abstract: An electronic device, with a plurality of logic stages for functional collaboration, is provided with selection means for selectively operating the plurality of stages to form either a sequential logic circuit or a combinatorial logic circuit. This enables conversion of sequential logic circuitry into combinatorial logic circuitry for the purpose of effective I.sub.DDQ -testing.

Abstract: A switched current memory circuit has an input to which an input current (i) is applied and which is connected via a switch (S1) to the drain electrode of a memory transistor (M). A second switch (S3) is connected between the memory circuit input and the source electrode of a grounded gate transistor (G) whose drain electrode is connected to the gate electrode of the memory transistor (M). The drain electrode of the memory transistor (M) is connected via switch (S2) to an output at which an output current (i.sub.o) is produced.The second switch (S3) provides zero-voltage switching which reduces the effects of charge injection on the current stored.

Abstract: The invention relates to an integrated circuit, comprising a number of independent clock domains. Seam circuits are provided in the interface signals paths between the clock domains in order to be able to isolate clock domains from each other during testing. Each seam circuit comprises a feedback loop having a multiplexer and a flip-flop feeding a first input of the multiplexer, a second input of the multiplexer being connected to the seam input, an output of the feedback loop being connected to the output; so that a first state of the multiplexer allows loading of a data bit in the feedback loop via the seam input, and a second state of the multiplexer freezes the data bit in the feedback loop.

Abstract: Compensating for phase nonalignment between VCO frequency divider and referenced frequency signal in a fractional-N PLL is provided by compensation implemented by a variable charge pump system. Phase comparator logic is configured to turn ON some of the charge pumps of the charge pump system early and the rest of the charge pumps later. This process effects an equivalent charge being turned ON at the exact point in time for properly compensating for the fractional charge.

Abstract: The invention relates to an integrated circuit comprising a dynamic CMOS Programmable Logic Array (PLA) with an AND plane and an OR plane. The invention also relates to a method for testing such a circuit. A PLA according to the invention is provided with means enabling detection of bridging faults. Adjacent lines can be driven to complementary logic levels. Crosspoint transistors can be switched off. In this way, bridging faults between lines give rise to an observable elevated quiescent power supply current (IDDQ).

Abstract: A functional circuit such as an OP-amp has a differential output. A common mode signal at the differential output is adjusted by means of a common mode feedback circuit coupled between the differential output and the common mode adjustment input. The common mode feedback circuit contains IGFETs, each having a channel and a backgate, each connection of the differential output being coupled to the backgate of a respective one of the IGFETS. Thus the voltages at the outputs influence the current through the channel. The sum of the currents determines a feedback to the common mode control input.

Abstract: A current memory cell comprises a fine MOS memory transistor (T1) and a coarse MOS memory transistor (T2) connected in series between two power supply rails. Such current memory cells are preferably designed so that the sum of the voltage drops across the coarse and fine memory transistors when diode connected is equal to the supply voltage. In order to achieve this while leaving flexibility in choosing the transistor saturation voltages an auxiliary power rail (V.sub.dda) is generated using as a reference the voltage drops across two diode connected transistors (T6, T7) which conduct a current equal to the bias current in the current memory cell (3).

Abstract: The switching time of a phase-locked loop (PLL) circuit can be reduced by increasing circuit bandwidth. A charge pump system is commonly used in the PLL circuitry to drive the voltage control oscillator (VCO). The increase in bandwidth intensifies the noise that is contributed by the charge pump system. To reduce charge pump noise, a chopper stabilizer circuit modulates the noise to a sufficiently high frequency so that a low-pass filter may filter out the modulated noise.

Abstract: An integrated circuit (IC) comprising an oscillator (OSC) has a first amplifier (AMP.sub.1) and a second amplifier (AMP.sub.2). The first and the second amplifier (AMP.sub.1, AMP.sub.2) each have a non-inverting input, an inverting input, and an output. The output of the first amplifier (AMP.sub.1) is connected to the non-inverting input of the first amplifier (AMP.sub.1) and also to the non-inverting input of the second amplifier (AMP.sub.2). The output of the second amplifier (AMP.sub.2) is connected to the inverting input of the first amplifier (AMP.sub.1) and also to the inverting input of the second amplifier (AMP.sub.2). The first amplifier (AMP.sub.1) is loaded with a capacitor (C) connected between the output of the first amplifier (AMP.sub.1) and an external power supply terminal (1). The second amplifier (AMP.sub.2) is loaded with a further capacitor (C.sub.F) connected between the output of the second amplifier (AMP.sub.2) and the external power supply terminal (1).

Abstract: A precharge circuit is provided that produces a reference voltage that can be used for the precharge process, without a direct current flow from the supply voltage. In a preferred embodiment of this invention, the precharge circuit precharges one bus to the supply voltage, and the other bus to ground potential, then, while each bus is capacitively charged to each of the supply and ground potentials, the buses are connected together. Assuming substantially equal capacitance on each bus, the resultant voltage on each bus will be half the supply voltage. A charge transfer effects the precharging of the buses to the supply and ground potential; the only current drawn from the power source is the transient current associated with a switch of capacitive loads.

Abstract: A method of manufacturing a semiconductor device which starts with a semiconductor wafer (1) which is provided with a layer of semiconductor material (4) lying on an insulating layer (3) at a first side (2). Semiconductor elements (5) and conductor tracks (14) are formed on this first side (2) of the semiconductor wafer (1). Then the semiconductor wafer (1) is fastened with this first side (2) to a support wafer (15), and material (18) is removed from the semiconductor wafer (1) from its other, second side (17) until the insulating layer (3) has been exposed. The method starts with a semiconductor wafer (1) whose insulating layer (3) is an insulating as well as a passivating layer. The semiconductor device must be provided with a usual passivating layer after its manufacture in order to protect it against moisture and other influences. In the method described here, such a passivating layer is present already before the manufacture of the semiconductor device starts.

Abstract: A digital to anologue converter comprises a plurality of current sources (T.sub.o -T.sub.n) and corresponding selection switches (D.sub.o -D.sub.n) which connect the current sources to an output (3). In order to enable a constant capacitance to be presented at the output (3) regardless of the input digital code a plurality of dummy current sources (T.sub.o -T.sub.n) which take the same form as the current sources (To-T.sub.n) are provided. The dummy current sources have associated selection switches ( D.sub.o -D.sub.n) which are operated by the logical inverse of the code applied to the current sources (T.sub.o -T.sub.n).

Abstract: An output driver circuit for coupling a logic circuit to load includes an input node, an output node for coupling to the load and a pull down switch which discharges the output node in response to a signal received at the input node. A current sink circuit includes a feeder transistor which provides current to the control terminal of the pull down switch to render the pull down switch conductive when the voltage at the output node exceeds a first threshold value between a logic high and a logic low. The feeder transistor is charged by a first charging path having a first impedance by which it takes a first time period to render the pull down switch conductive, the first impedance providing a low standby current when the voltage at the output node is below about the first value.

Abstract: The invention relates to a time domain method for obtaining transfer characteristics of a device under test (DUT). The method comprises the steps of applying a sine sweep and a cosine sweep to an input of the DUT, and measuring response signals at an output of the DUT. The sine sweep and cosine sweep together establish a complex input signal, whereby to each instant there is related a particular frequency. Similarly, the respective response signals together establish a complex response signal. The magnitudes and phases of both complex signals are calculated and the transfer characteristics of the DUT then follow from the magnitude ratio and the phase difference of the input signal and the response signal. The invention also relates to an arrangement for testing transfer characteristics of a DUT and to an integrated circuit comprising the necessary elements for testing a subcircuit contained therein.

Abstract: Mobility in an FET is used as a time standard to develop a resistance (or a transconductance or a current) reference which may be fully integrated and which is temperature stable to an arbitrary desired accuracy (or which varies with temperature in a desired fashion). The large temperature dependence of mobility is compensated (or adjusted to a desired variation characteristic) by applying a gate bias voltage having a predetermined variation in value with respect to temperature. In one embodiment the bias voltage of the FET is given a temperature dependence which results in the drain current of the FET being substantially constant with respect to temperature. This current is then used to charge or discharge a capacitor, yielding a precise R-C product which may be implemented fully in integrated form.

Abstract: A method for on-line handwriting recognition is based on a hidden Markov model and implies the following steps: sensing real-time at least an instantaneous write position of the handwriting, deriving from the handwriting a time-conforming string of segments each associated to a handwriting feature vector, matching the time-conforming string to various example strings from a data base pertaining to the handwriting, and selecting from the example strings a best-matching recognition string through hidden-Markov processing, or rejecting the handwriting as unrecognized. In particular, the feature vectors are based on local observations derived from a single segment, as well as on compacted observations derived from time-sequential segments.

Abstract: An electronic circuit comprises clocked functional circuits which receive a clock signal via a clock switch. The clock switch contains an enabled non-inverting driver which switches a connection between a power supply input and a clock output on and off under control of a clock signal only when the clock switch is enabled by an enable signal. The clock switch also contains a transmission switch coupled between a clock input and the clock output. The transmission switch is controlled from the enable input and makes a conductive connection between the clock input and the clock output only when the clock switch is enabled by the enable signal. As a result, transitions in the clock signal reach the functional circuits with less delay and power take-up needed to drive the clock signal is distributed so that there is less supply bounce.