Abstract: Protection among threads executing in the same address space of a computer system is provided without using virtual memory techniques. This is achieved by grouping the threads into protection domains, each of the threads in a protection domain having the same rights to access memory as the other threads in that protection domain, so that each thread in a protection domain can access all the information available to the others. At least one protection domain, referred to herein as the "system" domain, which typically is the protection domain of the operating system and has unrestricted access to the entire memory, is predefined prior to execution of any threads. Prior to execution, the single address space is divided into non-overlapping pages. Each page has at least one access permission set for it. Only threads that belong to a protection domain having permission to access a page may do so.

Abstract: A travel direction speaking system that is based on a portable laptop computer. The computer determines a route between an origin and a destination using an electronic map, and prepares driving instructions based on the route. Each driving instruction includes the spatial position (longitude and latitude) of a change in direction at which the driving instruction applies. The system includes a Global Positioning System (GPS) unit that provides the GPS determined position of the laptop computer. The computer compares the GPS position to the spatial position and outputs the corresponding driving instruction when the two positions are inferred to be within a specified range of each other. The range can be determined based distance or on a time period required to travel from the current position to a position at which the instructions should be spoken.

Abstract: Input apparatus for a data processing system. An input apparatus, for example a mouse or a track ball, comprises a member which is rotatable by manipulation by a user. The rotation causes a change of a magnetic field, which change is detected by a detector. The member in the apparatus in accordance with the invention comprises a non-homogeneous distribution of a soft-magnetic material which, upon rotation, changes a magnetic field externally applied to the member by a magnet.

Abstract: A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances I.sub.DDQ -testability with respect to known flip-flops.

Abstract: A parametrizable control module comprising first and second loadable counters, an electronic circuit comprising a plurality of such parametrized control modules, and a method for synthesizing such circuit.A parametrizable control module comprises a first and a second loadable counter. Both counters are fed by a primary clock input. The first counter feeds an enable input of the second counter. An output of the second counter feeds a module output. Furthermore, both counter outputs by means of a logical combining gate feed the enable input of the second counter as well as the module output. The module has a reset input that feeds the reset inputs of both counters and the enabling input of the second counter. The parametrizable control module is useful for multiple application in a controller circuit. Also a method for synthesizing such circuits is given.

Abstract: An (E)EPROM is provided in which information is written with hot electrons generated in the channel current at the source side of the channel instead of at the drain side, as is usual. To obtain the electric field distribution in the channel 6 necessary for this, the gate oxide 10 is provided with a thickened portion 13 adjacent the source zone 4 so that locally a strong lateral electric field is induced in the channel at higher gate voltages. An efficient charge transport of electrons to the floating gate 9 is obtained through this lateral electric field in the channel and the comparatively high electric field in the gate oxide. The thickened portion of the gate oxide may be obtained in a simple manner through thermal oxidation. To prevent the formation of strong fields at the drain side of the channel, the drain is preferably provided with an LDD structure 5a which adjoins the gate oxide. As a result, Fowler-Nordheim tunnelling through this thin gate oxide may also be used for erasing.

Abstract: A high pressure gas discharge lamp system includes a high pressure discharge lamp selected to have a lowest lamp resonant frequency above the audible, on a current basis above about 19 kHz and on a power basis of above about 38 kHz. The ballast circuit energizes the discharge device so as to have a fundamental frequency below the lowest lamp resonant frequency and above the audible, while keeping the magnitude of any harmonics above the lowest lamp resonant frequency sufficiently small so as to avoid acoustic resonance. By operating below the lowest lamp resonant frequency, greatly simplifying ballast construction and cost. According to one embodiment, the discharge vessel encloses a discharge space which is circular cylindrical and having a L:ID ratio of about 1:1 to maximize the lowest lamp resonant frequency.

Abstract: A computer system including a multi buffer data cache and method of caching data based on predicted temporal and spatial localities. A processor operates on operands under instruction control, the operands being stored in a main memory. The processor is coupled to the main memory via a data cache for prefetch and storage of operands referenced by the instructions. The data cache comprises an S-buffer for storing operands with strong temporal locality, and a P-buffer for storing operands with strong spatial locality. A control unit connected to the processor, the buffers and the main memory, determines what type of locality is involved in the operand referenced, based on whether the instruction accesses the main memory in a direct or indirect addressing mode as determined by a decoder unit of the processor, and governs operation of the buffer associated with the type of locality determined.

Abstract: A BiCMOS logic circuit having greater drive and speed at low voltage is provided. The logic circuit includes a switching device which allows the pull-down device of the logic circuit to be driven directly by an input signal without first having to switch a MOS device. The switching device conducts current between the input terminal of the logic device and the pull-down device when the output signal equals a certain value.

Abstract: A number of domestic audio/video apparatuses (10-14) are connected to a serial control bus (D2B, 16). Each apparatus is addressable via the bus as a device and contains functional elements addressable on subdevices. One apparatus (14) includes an on-screen display subdevice (41) and a first control subdevice (24). Subdevice status messages are defined whereby a control subdevice can ask to be informed of the status of a further subdevice (e.g. 26), and in particular to be informed automatically of any change in status without the need for continuous polling of subdevices. The subdevice status messages can be used to obtain early confirmation of a signal path being established through the system.

Abstract: A ballast for a gas discharge lamp includes a detection circuit which detects an operating state of the lamp in which the lamp current for the column discharge of one polarity is different from the lamp current for the column discharge of the other polarity by detecting the DC component of the voltage across the discharge lamp. The detection circuit includes (i) a device coupled such that a DC voltage is imposed there across when the lamp current is different for the column discharge according to one polarity verses the other polarity, and (ii) a sensing circuit for sensing the DC voltage across the device. The device may be a capacitive device, and in a particularly inexpensive implementation, is a DC blocking capacitor or a ballast capacitor. The sense circuit senses when the DC voltage across the device exceeds a threshold value, which may corresponds to fully-rectified state of the lamp or more favorably, to a lesser state of imbalance.

Abstract: Self-oscillation of a prescalar circuit is avoided by including offset generators on the inputs of the prescalar circuit. This ensures that when the transistors in one differential pair in the prescalar circuit transition from ON to OFF, the other differential pair of transistors will not transition. As a result, spikes are prevented in the differential pair that does not have a transition. A quadrature signal generator constructed with such a prescalar circuit provides an accurate output despite weak or non-existent input signals.

Abstract: An array of semiconductor diode lasers (11, 12) is a very suitable radiation source for various applications such as optical read and write systems and laser printers. Such an array includes a semiconductor body (10) with a substrate (1) and a layer structure provided thereon in which at least two lasers (11, 12) are formed which are mutually separated by a groove (20). In the known array, the groove (20) reaches down into the substrate (1), so that the lasers (11, 12) are electrically separated from one another. According to the invention, the array of lasers (11, 12) is provided with a groove (20) with a major portion (d) of its depth (D) which is situated within the substrate (1). As a result of this, the lasers (11, 12) of the array show a surprisingly low crosstalk. Preferably, the portion (d) of the groove (20) situated in the substrate (1) is at least 3 .mu.m deep. The best results are obtained with depths (d) of approximately 10 up to at most 40 .mu.m.

Abstract: In the manufacture of liquid-crystal display devices and other large-area electronics devices, electrostatic discharge damage (ESD) of tracks and other thin-film circuit elements can result during ion implantation and/or during handling. This damage is avoided by connecting the thin-film circuitry in a charge leakage path with gateable TFT links (45). These links (45) are TFTs (45) with a common gate line (7) for applying a gate bias voltage to control current flow through the links, e.g to turn off the TFTs (45) during testing of the device circuit. In accordance with the present invention the gateable links (45) in the leakage path are removed simultaneously by applying a sufficiently high gate bias (Vg2) to the common gate line (7) to break the links (45) by evaporating at least the channel regions (6) of the TFTs. A suitable thin-film structure is chosen for the TFTs (45) to facilitate evaporating their channel regions (6) in this manner.

Abstract: A method of manufacturing a semiconductor device whereby a photoresist layer is provided on a surface of a slice of semiconductor material, after which two photomasks corresponding to adjoining portions of a pattern to be formed in the photoresist are projected on the photoresist by means of a projection lens, with overlapping edges. Strip-shaped transparent end portions of the two photomasks which are situated within this edge and which overlap one another in projection are provided with strip-shaped connection patterns which overlap one another in projection and which exhibit a complementary transmittance in projection. To keep the quantity of computer data necessary for describing the photomasks comparatively small, the strip-shaped transparent end portions of the two photomasks overlapping one another in projection are provided at their edges only with strip-shaped connection patterns overlapping one another in projection.

Abstract: A one-shot current circuit generates a current for a desired period during an input signal transition, the desired period during an input signal transition being proportional to the edge rate of the input signal. The circuit includes a MOS transistor device which selectively conducts current between an input terminal and a current generating circuit. The current generating circuit can be a bipolar transistor having its base coupled to the input terminal and a main current path between a circuit output and a supply voltage.

Abstract: A new addition to log amplifiers for received signal strength indication in cellular telephony and telecommunications applications extends the large signal end of the signal strength curve by adding rectifiers to the input of an intermediate frequency amplifier, without degrading the noise figure or impedance characteristics thereof. The new addition to log amplifier outputs a signal which is linearly related to an input signal to the log amplifier.

Abstract: A circuit and method for improving the metastable resolving time in low-power multi-state devices, including binary latches in integrated circuits. Upon detection of a metastable condition at the outputs of the integrated circuit, an increase in energy is locally applied to the decision making portion of the circuit. The localized application of energy to the decision making circuit reduces the metastability time constant tau (.tau.), thereby causing the circuit to resolve more rapidly to a stable operating state.

Abstract: A database system comprises an individual station with berth means for receiving an optically readable information carrier with local information. The system reads the carrier and furthermore receives remotely supplied secondary information. It has a processor for processing both local information and secondary information to produce output information, and a user interface for presenting said output information to a user. In particular, the carrier has a read-only part, and a write part for storage of at least one decryption key. The processor is arranged for decrypting the secondary information using said at least one decryption key.

Abstract: A data prefetching arrangement for use between a computer processor and a main memory. The addresses of data to be prefetched are calculated by decoding instructions which have been prefetched by decoding prefetched instructions, the instructions having been in accordance with an intelligent prefetching scheme. The processor registers have two sections for respective access by the processor and a prefetch controller. The instruction registers may also contain an additional counter field which indicates the number of instruction cycles which must be executed before the register may be reliably utilized for prefetching data.