Abstract: A data reproduction apparatus and a data storage medium for synchronously reproducing multiplexed data with video, audio, and superimposed dialogue data compressed at a variable rate and performing various functions. Data are reproduced from the data storage medium using sector numbers, and data for negative sector numbers carried by some sectors are also reproduced. Multiplexing information indicating whether or not image, voice, and superimposed dialogue data is each multiplexed and information for the positions of access points used for data search and random access are stored in the positions represented by these negative sector numbers and reproduced so as to enable multiplexed data with video, audio, and superimposed dialogue data compressed at a variable rate to be synchronously reproduced and various functions to be executed.

Abstract: A television system performs beam convergence in video displays. The system is implemented through one or more convergence sensors, which are exposed to two distinct convergence test patterns. The output signals from the sensors when exposed to the two test patterns are used in beam convergence calculations. The test patterns are selected to reduce the dynamic range requirement for an A/D converter in the television system supplied with the sensor output signals. A low-pass filter circuit with selectable characteristics is also used to reduce the dynamic range requirement.

Abstract: A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 and the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity. If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

Abstract: A recording medium cartridge includes a memory circuit for storing information concerning signals recorded on the recording medium within the cartridge. The information is stored in the memory circuit in the form of a hierarchic data structure which includes a plurality of data packets having a predetermined form and length. Each data packet includes a code indicative of a level in the data structure to which the data packet belongs. At least some of the data packets include data indicative of starting and ending positions on the recording medium of recorded signals which the data packet represents. The hierarchic (or “tree”) data structure facilitates rapid retrieval and reproduction of the signals recorded on the recording medium, particularly when the recording medium is a magnetic tape. The tree structure also facilitates storage of information in connection with recording of additional signals on the recording medium.

Abstract: A data reproduction apparatus and a data storage medium for synchronously reproducing multiplexed data with video, audio, and superimposed dialogue data compressed at a variable rate and performing various functions. Data are reproduced from the data storage medium using sector numbers, and data for negative sector numbers carried by some sectors are also reproduced. Multiplexing information indicating whether or not image, voice, and superimposed dialogue data is each multiplexed and information for the positions of access points used for data search and random access are stored in the positions represented by these negative sector numbers and reproduced so as to enable multiplexed data with video, audio, and superimposed dialogue data compressed at a variable rate to be synchronously reproduced and various functions to be executed.

Abstract: A general purpose register stores a 16-bit fixed length instruction. A bypass circuit speedily outputs the result of a comparison instruction when the next conditional branch instruction is executed. An ALU performs a logic process and so forth. A high speed multiplying device/high speed dividing device performs an arithmetic operation at high speed. An address calculating portion calculates an address. An instruction decoder/pipeline controlling portion decodes an instruction and controls a pipeline. A dedicated control register is used as an interrupt stack pointer or the like. An interrupt controller performs a multiple interrupt process. A coprocessor bus is disposed independently from a data bus.

Abstract: A video card capable of being mounted in an information processing apparatus so as to enable suitable performance of a television conference system etc., wherein video data fetched into a video card from a camera by a capture operation is recorded in the first region of a DRAM and encoded at a signal processing unit. The encoded video data is recorded in the second region of the DRAM, sequentially transferred to a main memory of a notebook type PC, and transmitted to a network via a communication I/F card. The video data received from the network is stored once in the main memory, transferred to the fourth region of the DRAM of the video card, decoded at the signal processing unit, and recorded in the third region of the DRAM. Immediately before the next capture operation, the video data which was fetched into the first region of the DRAM before this and the received video data which has been recorded in the third region are displayed on a display via a VGA controller.

Abstract: A digital data recording method is provided where the efficiency of use of the recording medium storage area for recording data in a sequence is increased and a desired data can be retrieved at a higher speed. When a record n in an entity is terminated at the trailing end of a group N, a record n+1 following the record n is recorded in a group N+1. When a record n extends up to the group N+1, a header H2′ attributed to the group N and a front part of the record n as well as the preceding records 1 to n−1 are designated as another entity E2′. The remaining or rear part of the record n is designated as an entity E3′ and recorded in the group N+1 as added with a header H3′. Then, the record n+1 is designated as an entity E4 and recorded in the group N+1 as added with a header H4.

Abstract: A one-chip microcomputer including a Reduced Instruction Set Computer (RISC) type processor and one or more coprocessors for performing processes independent from said RISC type processor. The RISC type processor is coupled to the coprocessors via a coprocessor bus and is provided with a bypass circuit which facilitates execution of conditional branch instructions.

Abstract: An audio signal processor for processing 1-bit signals, comprises an input 40 for receiving a 1-bit signal, means 41, 42 for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n is greater than one, means 43 for determining the absolute value of the n-bit signal, means 46, 51 for producing a dynamics control signal dependent on the said absolute value, means 48 for applying the dynamics control signal to the 1-bit input signal, and means 49 for requantizing the dynamics controlled signal as a 1-bit signal and shaping the noise in the requantised 1-bit signal. Circuits for producing LOG base 2 and the corresponding anti-log are also disclosed.

Abstract: A signal reproducing apparatus for prohibiting copying or unauthorized use. The apparatus includes a copying management information decision circuit 19 for discriminating the state of the copying management information read out from each header of a data sector and within the TOC, a protect signal generating circuit 20 for generating a protect signal based on the discrimination signal and a mixing circuit 24 for mixing a protect signal in a vertical blanking period of an analog video signal D/A converted from digital video data reproduced from an optical disc D. The apparatus also includes a descrambling circuit 31 for descrambling the digital data based on the copying management information and a scrambling circuit 32 for descrambling the digital data. The apparatus enables prohibition of unauthorized analog copying and digital copying, inhibition of serial generational copying and prohibition of unauthorized analog and digital copying simultaneously.

Abstract: Audio processing apparatus comprises an audio processor operable to apply one or more processing operations from a set of audio processing operations to an input audio signal; adjustment controls for adjusting processing parameters associated with each of the set of processing operations; a display screen for displaying icons representing each processing operation of the set of audio processing operations; and a detector for detecting user operation of the adjustment controls associated with an a processing operation and, in response to such a detection, for displacing the display position of the icon associated with that processing operation.

Abstract: A video signal recording apparatus digitally records on a storage medium a video signal comprising an image signal, an audio signal, and an audio-associated information signal, the audio-associated information signal is included in a vertical blanking period of the video signal, the audio-associated information is collected, formatted, and digitally recorded in an area separate from areas where the image signal and audio signal are recorded.

Abstract: A repeat use data inserting apparatus for repeatedly inserting repeat use data into program data in accordance with appropriate timings. The apparatus comprises a data holding unit and a data multiplexing unit. The data holding unit holds the repeat use data made of a plurality of material data in the form of separately encoded streams. The data multiplexing unit multiplexes separately encoded streams of a plurality of material data constituting the program data during a period other than a data insertion period during which the repeat use data is inserted into the program data. The data multiplexing unit further inserts repeatedly the repeat use data into the program data during the data insertion period by multiplexing the separately encoded streams of the plurality of material data constituting the repeat use data held in the data holding unit.

Abstract: A bus management node 11 has a register for channels in use REG1 and a bus capacity register REG2. Before starting the synchronous communication, each node 12 transmits a read-out command to the register for channels in use REG1 in order to read out their contents for ascertaining the number of the un-used channel and the residual capacity. If there is any un-used channel and any residual bus capacity, the node 12 transmits write commands to these registers REG1 and REG2 so that the number of the channel to be in use and the capacity of the bus to be in use will be stored in the register for channels in use REG1 and the bus capacity register REG2. This enables bus management to be achieved easily in a system performing synchronous communication between plural nodes connected to the bus.

Abstract: A technique for selectively inhibiting a video recorder from recording and/or reproducing those television programs, which are not authorized for viewing. Authorization data associated with respective television programs that are receivable by the recorder and indication of whether that program is authorized for recording and/or reproduction, is received by the recorder prior to (or multiplexed with) the television program and is stored thereat. When the television program is received, the stored authorization data associated with that is read to determine if the received television program is authorized for recording and/or reproduction. If not, the recorder is inhibited from recording and/or reproducing that unauthorized television program.

Abstract: A RISC type microprocessor for implementing multi-stage pipeline processing. The RISC type microprocessor includes mode allocating means, interrupt controlling means and a jump instruction table. The mode allocating means is used for allocating a first mode for cyclically executing processes corresponding to a plurality of interrupts at predetermined intervals or a second mode for successively executing the processes corresponding to the interrupts. The interrupt controlling means is used for controlling the interrupts corresponding to the mode allocated by the mode allocating means, and is operable to save particular information to a stack upon occurrence of an interrupt and to fetch the particular information from the stack upon completion of the interrupt process. The jump instruction table is used in processing interrupts without stopping the multi-stage pipeline processing.

Abstract: A signal reproducing apparatus for prohibiting copying or unauthorized use. The apparatus includes a copying management information decision circuit 19 for discriminating the state of the copying management information read out from each header of a data sector and within the TOC, a protect signal generating circuit 20 for generating a protect signal based on the discrimination signal and a mixing circuit 24 for mixing a protect signal in a vertical blanking period of an analog video signal D/A converted from digital video data reproduced from an optical disc D. The apparatus also includes a descrambling circuit 31 for descrambling the digital data based on the copying management information and a scrambling circuit 32 for descrambling the digital data. The apparatus enables prohibition of unauthorized analog copying and digital copying inhibition of serial generational copying and prohibition of unauthorized analog and digital copying simultaneously.

Abstract: A device for measuring focusing characteristics of an optical pickup and/or an optical disc capable of measuring characteristics of focusing states with high accuracy by a simplified circuit. An arithmetic-logic unit 12d controls an offset supplying circuit 23 for applying an offset voltage to a focusing servo control signal. This arithmetic-logic unit 12d detects an error rate of the playback data in such a state in which the focusing position of the laser light is deviated by a pre-set offset amount. The arithmetic-logic unit 12d sequentially varies the offset voltage to repeat the above processing for detecting the error rate. The arithmetic-logic unit 12d approximates the relationship of the error rate to the offset amount by a quadratic curve based on detected data. The offset amount which minimizes the error rate is found from this equation of approximation.

Abstract: ATM data can be transferred via a highspeed serial data bus standardized by the IEEE 1394 format. In a data transferring apparatus for transferring data by employing a serial bus standardized by the IEEE 1394 format, an ATM cell transferring apparatus is comprised of an adding circuit for adding a predetermine header in order that an ATM cell used in a network defined by the ATM system is stored into the data field of the isochronous packet defined by the IEEE 1394 format.