Abstract: A negative charge pump circuit having a plurality of charge pump stages. Each charge pump stage has an input node and an output node and includes a pass transistor and a first coupling capacitor. The pass transistor has a first terminal connected to the input node, a second terminal connected to the output node and a control terminal connected to an internal node of the charge pump stage. The first coupling capacitor has a first plate connected to said output node and a second plate connected to a respective clock signal. Negative voltage regulation means are provided for regulating a negative output voltage on an output node of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit includes at least one negative voltage limiting means electrically coupling said output node of the negative charge pump circuit with the internal node of the last charge pump stage of the negative charge pump circuit.

Abstract: Switching losses in a DC-to-DC converter idling in a pulse-skipping mode are reduced by inhibiting any intervening turn-off command by a PWM control loop of the converter for as long as the current through the inductor of the converter remains below a minimum threshold value set by a dedicated comparator. The method is implemented by employing a comparator with a certain hysteresis and by logically masking the switching to a logic "0" of a high frequency clock (switching) signal of the converter for the entire period of time the current in the inductor remains below the minimum threshold.

Abstract: A circuit and method is provided for addressing memory cells in a memory device, including two series connected select gates having a node between them. A switching element is connected between the node and a ground voltage. A control signal is applied to a control input of the switching element to render it conductive while both of the select gates are non-conductive, so as to eliminate charge stored at a node between the two select gates. A particular application to an addressing circuit for use in a flash EPROM memory device is described.

Abstract: A sense amplifier circuit for a semiconductor memory device comprises a first current/voltage converter for convening a current of a memory cell to be read into a voltage signal, a second current/voltage converter for converting a reference current into a reference voltage signal, and a voltage comparator for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises a capacitive decoupler for decoupling the voltage signal from the comparator, and circuitry for providing the capacitive decoupler with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.

Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2.sup.n (n>=Z) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels.

Abstract: A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.

Abstract: In a flash-EEPROM array, the cells in each row are grouped into pairs connected to the same diffused source line and to two different diffused bit lines, and the adjacent pairs of cells are spaced so that, in each row, only one cell is connected to a respective diffused bit line. The array presents global bit lines in the form of metal lines, and each connected to a plurality of diffused local bit lines, at least one for each sector. For each sector and each global bit line, there are provided two diffused local bit lines connected to the same respective global bit line by selection transistors so that only one local bit line is biased each time.

Abstract: A nonvolatile memory having a cell comprising an N.sup.+ type source region and drain region embedded in a P.sup.- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.

Abstract: An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.

Abstract: In integrated structure sensing resistor for a power MOS device consists of a doped region extending from a deep body region of at least one cell of a first plurality of cells, constituting a main power device, to a deep body region of a corresponding cell of a second smaller plurality of cells constituting a current sensing device. The first plurality of cells and the second plurality of cells are formed using trench technology.

Abstract: A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator.

Abstract: A device integrated on a chip of a semiconductor material is disclosed which comprises an NPN bipolar transistor and an N-channel MOSFET transistor in an emitter switching configuration, both being vertical conduction types. The bipolar transistor has its base and emitter regions buried; the MOSFET transistor is formed with an N region bounded by the base and the emitter regions and isolated by a deep base contact and isolation region. To improve the device performance, especially at large currents, an N+ region is provided which extends from the front of the chip inwards of the isolated region and around the MOSFET transistor. In one embodiment of the invention, a MOSFET drive transistor is integrated which has its drain terminal in common with the collector of the bipolar transistor, its source terminal connected to the base of the bipolar transistor, and its gate electrode connected to the gate electrode of the MOSFET transistor in the emitter switching configuration.

Abstract: A low frequency amplifier comprising, in series, a first input stage, an intermediate amplifying stage and a final stage. The intermediate amplifying stage comprises a capacitor which is discharged when the amplifier is disabled, and is charged to a predetermined bias value when the amplifier is operative. To prevent voltage peaks at the output of the amplifier during the transient interval between the disabled and operating condition of the amplifier, a second input stage is provided which is only turned on during the transient interval, and is connected to the capacitor to detect its voltage and charge it. During the transient interval, the final stage is disabled. Upon the capacitor reaching the predetermined charge value, the second input stage practically turns itself off, and is then disabled; and, at the same time, the first input stage and the final stage are enabled to turn on the amplifier.

Abstract: A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

Abstract: An integrated structure protection circuit suitable for protecting a power device against overvoltages comprises a plurality of serially connected junction diodes, each having a first electrode, represented by a highly doped region of a first conductivity type, and a second electrode represented by a medium doped or low doped region of a second conductivity type. A first diode of said plurality has its first electrode connected to a gate layer of said power device and its second electrode connected to the second electrode of at least one second diode of said plurality, and said at least one second diode has its first electrode connected to a drain region of the power device. The doping level of the second electrode of the diodes of said plurality is suitable to achieve sufficiently high breakdown voltage values.

Abstract: A charge pump circuit including a number of pull-up stages connected in parallel with one another between a reference potential line and an output line. Each stage includes a capacitor having a first terminal connected to a charging and discharging node, and a second terminal connected to a pull-up node for switching between a first charging operating phase and a second charge transferring operating phase. The charging and discharging node is connected to the supply line via a charging transistor having a control terminal connected to a high-voltage bias node formed by the adjacent stage in the opposite operating phase, for charging the capacitor substantially up to the supply voltage.

Abstract: A coding scheme for transmitting messages particularly between computers is described. Messages are transmitted in packets which include at least a data portion and a terminator. Out of a predetermined set of symbols, sixteen data symbols and at least one control symbol is selected. The terminator token is generated to constitute the symbol and a six-bit symbol representing checking bits.

Abstract: A frequency doubler is described which is capable of receiving four input signals in quadrature and combining them to produce a pair of antiphase output signals at twice the input frequency.

Abstract: A method for generating a reset signal in an electrically programmable non-volatile storage device of a type which comprises a matrix of memory cells and a control logic portion being supplied a supply voltage and a programming voltage, and a threshold detection circuit adapted to detect a decrease in the supply voltage, provides for the signal applied to the control logic to be obtained as a change-over function between the output signal from the threshold detector and a reset signal generated during the power-on transient of the device.

Abstract: A double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy comprises a plurality of identical circuit blocks supplied with address signals and each one generating a respective selection signal which is activated by a particular logic configuration of said address signals for the selection of a particular row of the matrix; each one of said circuit blocks also generates a carry-out signal which is supplied to a carry-in input of a following circuit block and is activated when the respective selection signal is activated; a first circuit block of said plurality of circuit blocks has the respective carry-in input connected to a reference voltage; each of said circuit blocks is also supplied with a control signal, which is activated by a control circuitry of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row is addressed, to enable the activation of the r