Abstract: An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits, each one associated with a respective memory matrix portion or group of columns, and a plurality of programming load control circuits, each one controlling the activation of one respective programming load circuit according to the logic state of a respective data line carrying a datum to be programmed; the memory device comprises a group of redundancy bit lines and an associated redundancy programming load circuit; each programming load control circuit comprises decoding means supplied with signals which, when a defective column address is supplied to the memory device during programming, are generated from a matrix portion identifying code stored in a non-volatile register wherein the defective column address is stored, and switch means responsive to a decoded signal at the output of said decoding means to enable the activation of the redundancy programming load

Abstract: A circuit for generating positive and negative boosted voltages, comprising first and second voltage booster circuits, respectively for positive and negative voltages, which have output terminals interconnected at a common node. It comprises two tristate logic gate circuits for coupling said voltage booster circuits to a positive supply voltage generator and additional tristate logic gate circuits for driving the phases of charge pump circuits incorporated into the booster circuits. This voltage generating circuit may be integrated in single-well CMOS technology.

Abstract: High-performance operational transconductance amplifier monolithically integrable with CMOS technology comprising a differential input stage connected to a pair of cascode stages and a differential output stage. The output stage comprises two output transistors whose gate terminals are connected to nodes for connection of the input stage and the cascode stages. The output terminals of the amplifier are connected to intermediate nodes of the cascode stages through capacitors.