Abstract: Computer-implemented methods, systems, and computer program products for autonomic recovery of messages are provided. A computer-implemented method includes creating a temporary file for a communication session. The temporary file identifies a communication partner to the communication session and a start time of the communication session. The computer-implemented method also includes monitoring the communication session. Upon the occurrence of a triggering event, the computer-implemented method includes logging the time of the triggering event in the temporary file, logging the time of any messages received after the time of the triggering event, and storing the messages in the temporary file. The computer-implemented method further includes presenting the messages in response to initiation of another communication session with the communication partner.

Abstract: A method of manufacturing a liquid crystal display includes; forming a mother substrate assembly by disposing a liquid crystal mixture layer having liquid crystals and a light curable alignment supplement between a first mother substrate and a second mother substrate of a liquid crystal display, and disposing a light curable sealant surrounding the liquid crystal mixture layer, pre-tilting liquid crystal molecules of the liquid crystal mixture layer by applying a voltage to the first mother substrate and the second mother substrate, and simultaneously hardening the alignment supplement and the sealant by radiating light to the mother substrate assembly while applying the voltage to the first mother substrate and the second mother substrate.

Abstract: An output voltage monitoring circuit monitors an output voltage of a capacitor charging circuit. A first sample-and-hold circuit samples and holds a voltage of a connection point of a primary coil of a transformer and a switching transistor. A first monitoring comparator compares output of the first sample-and-hold circuit with a predetermined first reference voltage. When the output of the first sample-and-hold circuit exceeds the first reference voltage, a signal processor executes predetermined signal processing. The first sample-and-hold circuit starts a sampling period after a predetermined first time has elapsed after the switching transistor is turned OFF. When a voltage drop across a detection resistor reaches a third reference voltage, the first sample-and-hold circuit ends the sampling period.

Abstract: Process for preparing a compound of the formula (I) R1-S(O)x—S(O)yR2 in which R1 represents a molecular hydrocarbon radical which can be substituted and/or interrupted by one or more atoms and/or by one or more groups containing one or more atoms, said atoms being selected from N, O, P, S, Si and X, where X represents a halogen; R2, independently of R1, represents a carbon-containing group or a molecular hydrocarbon radical which can be substituted and/or interrupted by one or more atoms and/or by one or more groups containing one or more atoms, said atoms being selected from N, O, P, S, Si and X, where X represents a halogen, and x and y are selected from 0 and 1 in such a way that the sum of x and y is not more than 1, characterized in that a compound of formula (II) R1-S(O)x—R3-Si(R4)(R5)(R6) in which R3 represents a hydrocarbon chain of two carbon atoms, which is optionally unsaturated and/or substituted, and R4, R5 and R6, which are identical or different, each represent, independently of one another, a

Abstract: A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Abstract: An apparatus for implementing a write assist for a memory array includes a common discharge node configured to provide a discharge path for precharged write data lines and bit lines selected during a write operation of the memory array; negative boost circuitry configured to introduce a voltage lower than a nominal logic low supply voltage onto the common discharge node following the discharge of the common discharge node, write data lines and bit lines; and a clamping device coupled to the common discharge node, the clamping device configured to limit the magnitude of negative voltage applied to common discharge node by the negative boost circuitry so as to prevent activation of non-selected bit switches.

Abstract: A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

Abstract: A refrigeration circuit having a system charge and a system charge storage area. The system charge area has a condenser having a set of micro-channel heat exchanger coils. The condenser is appropriately sized to receive a first volume of the system charge. There is a compressor for compressing the system charge from an expanded state to a compressed state. There is a sealed refrigerant charge holding area fluidly connected to the condenser and the compressor. The sealed refrigerant charge holding area is appropriately sized for storing a second volume of the system charge during a system pumpdown. A receiver is fluidly connected to the sealed refrigerant charge holding area. The receiver is appropriately sized to receive a third volume of the system charge during a system pumpdown.

Abstract: Methods, systems and computer program products for reducing database workload volume. Methods include collecting a sequence of database commands directed to a single database record in a database. The sequence of database commands are reduced to a net result by combining database commands within the sequence of database commands. The net result is written to an output entity when the net result includes a database command.

Abstract: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

Abstract: An organic light emitting device and a manufacturing method thereof, including a first signal line and a second signal line intersecting each other on an insulating substrate, a switching thin film transistor connected to the first signal line and the second signal line, a driving thin film transistor connected to the switching thin film transistor, and a light emitting diode (“LD”) connected to the driving thin film transistor. The driving thin film transistor includes a driving control electrode and a driving semiconductor overlapping the driving control electrode, crystallized silicon having a doped region and a non-doped region, a driving gate insulating layer disposed between the driving control electrode and the driving semiconductor, and a driving input electrode and a driving output electrode opposite to each other on the driving semiconductor, wherein the interface between the driving gate insulating layer and the driving semiconductor includes nitrogen gas.

Abstract: A method of displaying images on an electrophoretic display (“EPD”) panel includes displaying a (K)-th image on the EPD panel including a plurality of electrophoretic particles, wherein K denotes a natural number. Then, when an interrupt signal for converting images is inputted during one of a plurality of driving intervals, a charge of the electrophoretic particles is compensated, which is charged in correspondence with the (K)-th image displayed on the EPD panel before the interrupt signal is inputted, and then a (K+1)-th image is displayed on the EPD panel. Thus, when the interrupt signal is inputted during one of the driving intervals displaying the (K)-th image data, the charges that are charged in the particles are compensated in correspondence to the (K)-th image data, and then the (K+1)-th image is displayed so that display quality may be enhanced.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.

Abstract: A method of analyzing production steps includes inputting application data associated with a production process having a plurality of process steps into a memory with each of the plurality of process steps including a plurality of tools. The method also includes loading process data associated with one of the plurality of process steps into the memory, performing a tool commonality analysis on each of the tools associated with the at least one of the plurality of process steps, identifying all tool-to-tool differences for the at least one of the plurality of process steps, performing a tool stratification analysis to identify one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps, and stopping the one of the plurality of tools that provides the largest variance contribution to the at least one of the plurality of process steps.

Abstract: Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.

Abstract: A method of reporting search results of a collection of data is disclosed. The method includes obtaining a hash function and a pattern of data for which to search within the collection of data and searching the collection of data for one or more strings of data that match the pattern. In response to finding one or more strings of data that match the pattern, the method further includes hashing each string that matches the pattern of data with the hash function and creating one or more rows of a results table. Each row of the results table corresponds to one string of data that matches the pattern of data and includes the corresponding hashed string of data.

Abstract: A method comprising, defining a social network U={u, u?, . . . }, defining a set of relationships between users O?U×U, defining a set of attributes of the social network A={a1, a2, . . . }, defining a set of contacts of the user u, defining a user profile of the user u Iu=Au?Uu, defining a metric M={m1, m2, . . . }, receiving a rating of a metric of user u? from the user u, defining a condition c?C, defining a set of elements Z={z1, z2, . . . }, receiving a request for access to Iu from user u?, determining authorization for user u? to access a subset of Iu by an access control function U×U×Pow(R)×C?Pow(Iu×Z), and outputting a subset of Iu to user u? as determined by the access control function.

Abstract: A thermo-electric semiconductor device is provided. The thermo-electric semiconductor device includes: a first electrode layer; a spacer layer formed on the first electrode layer and having a plurality of pillars with a uniform height, the plurality of pillars thermally grown and protruded on a surface of the spacer layer; and a second electrode layer formed over the spacer layer in such a manner as to contact tops of the protruded pillars.

Abstract: Disclosed herein is a method of using megestrol acetate. In one embodiment, the method comprises informing a user that megestrol acetate is metabolized by a cytochrome p450 isozyme. In another embodiment, the method comprises obtaining megestrol acetate from a container associated with published material providing information is metabolized by a cytochrome p450 siozyme. Also disclosed are articles of manufacture comprising a container containing a dosage form of megestrol acetate, wherein the container is associated with published material informing that megestrol acetate is metabolized by a cytochrome p450 siozyme, a method of treatment, and a method of manufacturing a megestrol acetate product.