Abstract: An instruction caching system comprises meta-instructions which are contained within the program being executed. A meta-machine, which is a small segment of software, executes the meta-instructions and passes control to the processor itself at appropriate times to execute blocks of instructions from the instruction cache.

Abstract: An interpolator array having a plurality of interpolator array cells is provided for receiving first and second input values to be interpolated and an interpolator weight term, to provide an interpolated output. A bit of each of the two input values to be interpolated is received by an interpolator array cell and applied to a selecting circuit within a cell of the interpolator array. Additionally, an interpolation weight bit of the interpolation weight term is applied to the selection circuit. The selecting circuit applies either the input bit of the first input value or the input bit of the second input value to an adder within the interpolator cell in accordance with the value of the interpolation weight bit. An interpolator array cell also receives a partial product input and a carry-in input and applies these additional inputs to the adder. The adder provides a partial product output and a carry-out in accordance with the applied inputs.

Abstract: In a method of encoding a sequence of frames of a full color digital motion video signal, the initial frame of the sequence is selected for encoding at multiple levels of resolution. The initial frame becomes a previous target image and a previous reconstructed image is formed by storing a reconstructed image. After processing the initial frame, each subsequent frame of the sequence of frames is then selected as the target image. Displacement vectors, representing the magnitude and displacement between regions in the target image being processed and corresponding regions in the previous target image are provided. Each displacement vector is applied to a corresponding region in the previous reconstructed image to form a predicted image. The displacement vectors are encoded using a binary tree technique with off-center splits.

Abstract: At least one selected image of a digital video signal is encoded at multiple levels of resolution. For each level of resolution, a correction image is formed by subtracting the value of each pixel in a reference image of that resolution level from the value of each corresponding pixel in the selected image of that resolution level. The correction image is quantized and encoded. A decoder decodes the encoded quantized correction image for each resolution level. The value of each pixel in the decoded correction image having the lowest resolution is added to the value of each corresponding pixel of a reference image having the same resolution to form a result image of the lowest resolution. This result image is expanded to the next higher level of resolution. The value of each pixel in the expanded result image is added to the value of each corresponding pixel in the decoded correction image of the same resolution level to form a result image of that resolution level.

Abstract: A video signal processing system includes a memory for holding digital data, input and output channel circuitry for reading data from and writing data to the memory and processing circuits for processing data read from the memory to produce data to be written to the memory. Each of the input and output channels produces two types of memory request signals, a normal request signal and an urgent request signal. The normal request signal is produced to gain access to the data in the memory for normal read and wire operations. The urgent request signal is produced to access the memory when the processing circuitry is in a paused state waiting either to obtain data from the input channel or to provide data to the output channel. The normal read and write request signals are handled with substantially equal priority by first scheduling circuitry. The urgent request signals are handled by second scheduling circuits according to a fixed priority scheme.

Abstract: A full motion color digital video signal is compressed, formatted for transmission, recorded on compact disc media and decoded at conventional video frame rates. During compression, regions of a frame are individually analyzed to select optimum fill coding methods specific to each region. Region decoding time estimates are made to optimize compression thresholds. Region descriptive codes conveying the size and locations of the regions are grouped together in a first segment of a data stream. Region fill codes conveying pixel amplitude indications for the regions are grouped together according to fill code type and placed in other segments of the data stream. The data stream segments are individually variable length coded according to their respective statistical distributions and formatted to form data frames.

Abstract: A video signal processor includes circuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuitry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.

Abstract: A method of encoding digital data using a variable-length code is disclosed. Using this method, the data are first transformed so that the values generally correspond to a family of statistical distributions, in this case, negative exponential distributions. The transformed data values are then analyzed to develop parameters describing a particular variable length code. The transformed data values are encoded using this code and the parameter values are concatenated onto the code to aid in the decoding operation.

Abstract: Digital image data is encoded using a variable-length code which is described by a group of parameter values. Each parameter value describes a set of code values; each code value corresponds to a possible value of the data which is to be encoded. When the data is encoded, the parameter values are appended to the encoded data. A decoder stores the parameter values into a memory and then combines data values derived from the encoded data with parameter values from the memory to generate decoded data values. Each code word includes a prefix which indicates a number of successive parameter values which are to be summed, and a population index which is to be added to the summed parameter values to produce a decoded data value.

Abstract: A method for computing, in a computer with a television terminal, spatially transformed locations for samples in three-dimensional image space, of which a two-dimensional view is afforded on the television terminal. The spatial transformation of sample locations allows objects to be rotated, precessed or translated on the viewing screen of the television terminal. The original locations of samples are considered to be along a path in image space proceeding from a starting point sample. A spatial transform of the starting point is computed. The successive vector differences between successive samples along the path are determined, and the various values of these vector differences are spatially transformed. Spatially transformed samples are successively generated along the spatially transformed path in image space by successively adding the spatially transformed vector differences to the spatially transformed starting point sample, in an accumulation procedure.

Abstract: A full motion color digital video signal is compressed, formatted for transmission, recorded on compact disc media and decoded at conventional video frame rates. During compression, regions of a frame are individually analyzed to select optimum fill coding methods specific to each region. Region decoding time estimates are made to optimize compression thresholds. Region descriptive codes conveying the size and locations of the regions are grouped together in a first segment of a data stream. Region fill codes conveying pixel amplitude indications for the regions are grouped together according to fill code type and placed in other segments of the data stream. The data stream segments are individually variable length coded according to their respective statistical distributions and formatted to form data frames.

Abstract: A video signal processor includes a stored-program controller which concurrently reads two instruction values from a program memory during each instruction cycle. The next instruction used by the video signal processor is selected from between these two values. If the current instruction indicates a conditional branch operation, the value of one of a plurality of conditions internal to the video signal processor determines which of these two instructions is selected. Otherwise, a value provided by the current instruction itself determines which of the two instructions is selected. This configuration of the stored program controller implements a conditional branch facility in which there is no delay in fetching an instruction for either value of the selected condition.

Abstract: In a process of forming vias for multilevel interconnects used in integrated circuits, a layer of a first metal is formed on a semiconductor substrate. A layer of a second metal is formed on the first metal layer. The second metal layer is etched in a predetermined via pattern with a second etchant which reacts with the second metal and which is substantially unreactive with the first metal. The first metal layer is then etched with a first etchant which reacts with the first metal and which is substantialy unreactive with the second metal or with the semiconductor substrate in order to form a predetermined contacting relationship with the predetermined via pattern. This process may be used to generate second and subsequent levels of vias and interconnects which can be used to contact metal layer at any level directly to the substrate by building via posts from the substrate to any desired metal layer.

Abstract: In a quadrature amplitude modulator, two binary, synchronous data signals representing four possible phase states of a carrier signal are sampled and respectively fed into two shift registers comprising part of a finite impulse response lowpass filter. The samples in each corresponding pair of stages in the shift registers are multiplexed at twice the carrier frequency. Each multiplexer output is then added modulo-two to a binary signal at the carrier frequency using exclusive-OR gates. The gate outputs are weighted in a desired fashion and summed and converted to an analog signal which exhibits a preferred spectral shape. This approach enables the quadrature amplitude modulation function to be included within the structure of the finite impulse response lowpass filter. The binary synchronous nature of the input data enables the structure of the filter to be simplified and the number of multiplexers and modulo-two adders to be reduced to a number equal to the number of bits stored from the input sequences.

Abstract: An applique of a prepatterned film of alpha particle resistant material, such as polyimide, is applied to a semiconductor wafer. The prepatterned film covers only the critical areas e.g. those affected by alpha particle impingement. Bond pads and scribe streets are not covered by the applique.

Abstract: A fabrication process for integrated circuits having linear bipolar transistors and other circuit elements. The process defines collector contact 32, base 34, and isolation 36 regions in one masking operation. Subsequent masking layers of photoresist 40, 42, 46 are used to shield selected regions during implantation of exposed regions. Circuit density is improved through the use of aluminum doped isolation regions 36. The base region is doped in a single ion implantation step, which is followed by low temperature deposition of a covering oxide layer 48.

Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.

Abstract: A method for producing an improved capacitor in MOS technology utilizing a thin layer oxide dielectric to improve the active/parasitic capacitance ratio while maintaining a high breakdown voltage and a low leakage current.A polycrystalline silicon layer is formed over a silicon dioxide field region on a wafer of semiconductor silicon. Phosphorus ions are implanted in the polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV. The surface of the polycrystalline silicon layer is oxidized to form an interpoly oxide, utilizing an oxidation temperature which, for the implant dosage of phosphorus ions used, is sufficient to make the interpoly oxide layer approximately 770 Angstroms thick. The structure is then annealed at a temperature of approximately 1100.degree. C. in oxygen and HCl. A second polycrystalline silicon layer is formed over the interpoly oxide layer, and the process completed in the conventional manner.

Abstract: The present invention is an improved active load which eliminates the current imbalance between the collectors of the emitter-coupled input transistors. The circuit includes a pair of first and second emitter-coupled transistors with their collectors coupled to a current source which supplies substantially equal currents to the collectors of the two transistors. The collector of one of the emitter-coupled transistors is coupled to the base of a third output transistor. A fourth transistor is coupled between the collector of the output transistor and the supply voltage. Finally, the circuit includes means for supplying the base current to the fourth transistor such that the base current of the fourth transistor and the third output transistor are substantially equal and the collector currents of the first and second emitter-coupled transistors remain substantially equal, resulting in negligible offset current and high open loop gain.

Abstract: A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the bases and collectors of the two transistors Q1 and Q2 forming the memory cell. The metal silicide 30 shorts PN junctions 29 in polycrystalline 23. Two further strips 50 and 52, each comprising a sandwich of P type polycrystalline silicon 42, metal silicide 45, and N conductivity type polycrystalline silicon 47, are formed to couple the cross-coupled bases and collectors to respective diodes 60 and 65. The diodes 60 and 65 are formed by depositing metal 62 and 64 in electrical contact with the underlying N type polycrystalline silicon 47.