Abstract: A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PH junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

Abstract: A method of introducing a controlled flow of vapor from a high pressure sublimation chamber into a low pressure vapor deposition reactor, said vapor being derived from solid source material preferably, but not necessarily, having a vapor pressure above about one (1) Torr at a temperature not exceeding about 350.degree. C. The method comprises controllably heating the source material to a temperature sufficient to produce vapor therefrom at a desired pressure, and then controllably transferring the vapor through vapor transmission means to the vapor deposition reactor. During such transfer, the transmission means is maintained at a temperature sufficient to prevent condensation of the vapor therein during transfer. The vapor is delivered to the reactor in a pure state and is not mixed with any carrier medium.

Abstract: A method for forming a substantially planar inorganic dielectric layer over a predetermined pattern of electrical interconnects comprises the steps of reacting phosphoric acid and a trivalent metallic halide compound with an aliphatic solvent to form a coating fluid. The coating fluid is then spun onto the semiconductor device to form a layer over the electrical interconnect. The resultant device is then baked at a first temperature to drive off the solvent and then baked at a second, higher temperature, in order to promote the glass forming reaction. This process is repeated as required to form a coating layer having a thickness which exhibits levelling characteristics of such high quality that fine topography can be carried out on succeeding layers of metal in order to form additional interconnect layers with precision.

Abstract: The two transistors of a bipolar flip-flop structure are interconnected by using a polycrystalline silicon/metal silicide sandwich structure. The polycrystalline silicon is doped to correspond to the underlying regions of the transistor structures, and undesired PN junctions created thereby are eliminated by depositing refractory metal silicide on the upper surface of the polycrystalline silicon.

Abstract: A programmable charge coupled device transversal filter 5 includes a charge coupled device register 10 for receiving and delaying incoming analog signals, a series of floating gate charge detectors 15, a corresponding number of sets of binary scaled capacitors C.sub.0, . . . 2C.sub.0 . . . 2.sup.n C.sub.0, an output circuit including a positive and negative bus coupled to a differential amplifier, and mask or otherwise definable electrical connections for connecting selected ones of the scaled sets of capacitors between the floating gate 15 corresponding to that set and one of the positive and negative buses 22 and 23.

Abstract: A process for fabricating self-aligned regions of metal silicide on bipolar integrated circuits having self-aligned polycrystalline silicon emitters and base contacts includes the steps of depositing a layer of polycrystalline silicon across the surface of the structure, patterning the polycrystalline silicon to define the emitters and base contacts as well as resistors and diodes, heating the structure to transfer desired conductivity dopants from the polycrystalline silicon into the underlying structure, forming a protective layer over those regions of the structure where metal silicide is not desired, depositing a layer of refractory metal across the entire structure, and reacting the refractory metal with the underlying silicon to form metal silicide.

Abstract: A lead wire bonding machine is described for ball bonding the end of a lead wire held in a bonding tool to a die pad of an integrated circuit chip and for wedge bonding a segment of the lead wire spaced from the ball bond to a lead frame finger during successive ball bond wedge bond cycles. The bonding machine includes a variable linear drive such as a solenoid or small linear motor coupled to the bonding head for applying the first bond force to the bonding tool during ball bonding and the second bond force to the bonding tool during wedge bonding. A control circuit coupled to the solenoid or other variable linear drive delivers a first current having a desired profile or amplitude wave envelope for applying the first bond force with a first force profile during ball bonding to die pads and by delivering a second current having a desired profile or amplitude wave form for applying the second bond force with a second force profile during wedge bonding to lead frame fingers.

Abstract: An improved lead wire ball bonding machine for bonding wire leads between an integrated circuit chip and the lead frame on which the chip is mounted is provided with a bonding tool position sensor coupled to receive the Z-motion velocity waveform signal to the servo motor which drives the bonding head and bonding tool. This sensor detects the signal level and direction of change or polarity of the Z-motion velocity waveform signal for determining the location of the bonding head and bonding tool. The bonding tool position sensor is coupled and adjusted for generating a first output signal corresponding to a first location of the bonding head and bonding tool during motion downward to the die pad of an integrated circuit chip prior to contact by the bonding tool and lead wire for ball bonding.

Abstract: An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

Abstract: A microprocessor integrated circuit (50) has a read only memory (ROM) (400) which is X and Y addressible and is word, bit and page oriented. The microprocessor integrated circuit (50) has a main injector bus (602) and a ground return bus (604) with a branch ground bus (608) connected to the ground return bus (604) through a ground-balancing resistor (610) in a data path. The circuit (50) has a register file (82) with registers (622) connected to a local bus (604). The local busses (604) are connected to a main bus (602) through a multiplexer (605). The microprocessor integrated circuit (50) includes a D-type flip-flop circuit (700) with asynchronous clear and preset. A latch dual port random access memory (RAM) circuit (900) is employed in the register file (82) of the microprocessor integrated circuit (50).

Abstract: An improved TTL tristate device with reduced output capacitance incorporates an active discharge sequence of three elements including first and second active transistor elements (Q8, Q7) in an inversion coupling and a third passive element comprising a passive diode cluster (D3, D4, D5) coupled between the base of the second transistor element (Q7) and the enable gate. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor (Q7) when the enable gate (A) is at high potential for operation of the output device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor (Q7) when the enable gate (A) is at low potential for operation of the output device in the high impedance third state with reduced output capacitance.

Abstract: A circuit and method for enabling/disabling a differential signal output from a memory device, such as a bipolar static random access memory, is disclosed. A split bias, current steering circuit includes a first differential amplifier for steering a current I.sub.D along a first current path when a first selected differential input signal, corresponding to a first logic state, is coupled to a first input terminal of said first differential amplifier; and includes a second differentialamplifier for steering current I.sub.D along a second current path when a second selected differential input signal, corresponding to a second logic state, is coupled to a second input terminal of said second differential amplifier. An output stage produces a selected logic output signal according to which of said first and second current paths is selected to steer current I.sub.D. A split bias enable/inhibit stage provides controlled operation of the first and second differential amplifiers.

Abstract: A microprocessor data processing system (1700) includes system units (50, 1704) connected to a bus (1702), with a bus arbiter (1712) and a protocol for assigning bus access to the system units (50, 1704). The microprocessor (50) executes both arithmetic operations and floating point operations. A microcontrol store (162) stores common instructions usable in different floating point operations. A PLA (180) supplies addresses to microcontrol store (162) and provides a signal indicating floating point instruction type. The microprocessor (50) includes a pending interrupt register (250) connected to mask and enable logic (268). The mask and enable logic (268) is connected to a priority encoder (278), which is connected to an interrupt latch (282). The latch (282) supplies outputs to generate a current state storage address.

Abstract: A high speed error correcting random access memory system includes a circuit for generation of a plurality of parity bits from a predetermined combination of data bits of a data word being stored in a random access memory such that these parity bits are stored in memory along with said data bits, and for outputting the data word from said memory system, including correcting for any single bit error in the data word, by a circuit that generates a check word from the data word bits and parity word bits stored in the memory, whose state indicates if any of the data bits are in error, and, if so, proceeds to correct any such erroneous bit. The system also includes a circuit for inserting an erroneous bit of data in memory after the parity bits have been generated, to check operation of the check word generating and output data word correction circuit. The operation of the check word generating circuit can also be suspended so as to enable uncorrected data words to be output by the memory system.

Abstract: A method and circuits are described for sensing and detecting bond attempts and weld attempts during bonding and welding of lead wire. The method and circuitry are particularly applicable for detecting missed ball bonds and missed wedge bonds during bonding of lead wire between the die pad of a microcircuit chip and the lead frame on which the chip is mounted. A sensor (30) or sensing circuit (42) senses the different characteristic electrical condition of the lead wire (11) following a ball bond attempt and following a wedge bond attempt. A bond attempt indicator (45) indicates high resistance in the lead wire following a missed ball bond while weld attempt indicator (46) indicates low resistance in the lead wire (11) following a missed wedge bond. The lead wire (11) is isolated from uncontrolled contacts with ground potential while the lead wire is held in the bonding tool and bonding machine.

Abstract: A lateral transistor structure having a self-aligned base and base contact is provided, together with a method for fabricating such a structure in which the base width is controlled by lateral diffusion of an impurity through a polycrystalline silicon layer. The resulting zone of impurity changes the etching characteristics of the layer and permits use of a selective etchant to remove all of the layer except the doped portion. The doped portion may then be used as a mask to define the base electrical contact, which in turn is used to provide a self-aligned base for the transistor. Dopants introduced on opposite sides of the base electrical contact create the emitter and collector.

Abstract: A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the bases and collectors of the two transistors Q1 and Q2 forming the memory cell. The metal silicide 30 shorts PN junctions 29 in polycrystalline 23. Two further strips 50 and 52, each comprising a sandwich of P type polycrystalline silicon 42, metal silicide 45, and N conductivity type polycrystalline silicon 47, are formed to couple the cross-coupled bases and collectors to respective diodes 60 and 65. The diodes 60 and 65 are formed by depositing metal 62 and 64 in electrical contact with the underlying N type polycrystalline silicon 47.

Abstract: A digital and linear dynamic ignition control apparatus comprising a burn-time counter, a pre-dwell counter, a current limit counter, engine speed detection apparatus, a biasing circuit and an excess current limit circuit is provided for controlling the start of a dwell in each ignition period. In operation, a current limit adjust window is established for each period. The time of the termination of a dwell in the period relative to the current limit adjust window established for the period starts the dwell in the next period relative to the beginning of the next period at a time calculated to optimize engine performance and minimize energy losses. In general, rapid acceleration in a period starts the dwell earlier in the next period to insure adequate charging of the ignition coil. Conversely, rapid deceleration in a period starts the dwell later in the next period to minimize energy losses.

Abstract: Decoding apparatus for an integrated circuit memory having normal rows of memory cells 10 and at least one selectively connectable redundant second row of memory cells 31 for being connected in place of one of the first rows 10 includes a redundant decoder (transistors 32, 33. . . n) connected to each of the redundant rows 31, the redundant decoder including a plurality of selectable connections (F.sub.1, F.sub.2 . . . F.sub.n) for creating an address for each of the at least one redundant rows 31; a control signal generating circuit (gates 45, 46, and 47) for generating a control signal of a first state until an address is supplied to the memory and of a second state if any of the redundant rows 31 are selected by the address, and another decoder (transistors 23 and 39) connected to receive control signal .phi..sub.C from the generating circuit for controlling normal rows 10 and the redundant row 31 in response thereto.

Abstract: MOS Control circuitry for incorporation on a microcomputer IC chip for assuring adequate power to maintain the data in an associated static random access memory. A rechargeable battery provides standby power, and the voltage level of the battery is compared with the microcomputer V.sub.cc supply. Whenever V.sub.cc drops below a predetermined level, such as the standby battery voltage level, the circuitry disconnects the V.sub.cc from the memory input power and replaces it with standby battery power. When V.sub.cc is returned to the system, a gate applies a trickle charge to the battery.