Abstract: A process is disclosed for fabricating complementary n and p channel insulated gate field effect transistors. The process uses two layers of polycrystalline silicon 32 and 44 to provide electrical interconnections, and allows the formation of microcapacitors between the two layers of polycrystalline silicon. In addition silicon dioxide and silicon nitride, and two layers of photoresist, are used as masks against heavy boron implantations. The reliability of ohmic connections between aluminum 50 and contact regions in the substrate is enhanced by providing additional dopant to the contact regions. In this way, the junction depth is increased and electrical defects caused by metal spiking are minimized.

Abstract: A process is described for fabricating spacers of a desired thickness of filters, the spacers to be used in separating the filter from an underlying image sensing device. The process includes the steps of forming a pattern of electrically conductive material on one surface of the filter, depositing dry resist to the desired thickness over all of the filter except on the electrically conductive pattern, depositing additional electrically conductive material on at least the electrically conductive pattern, and removing the dry resist.

Abstract: Base resistance in an integrated injection logic cell is reduced by providing a low resistance conductive path over the device cell and contacting the base regions of vertical transistors in the cell. In fabricating the I.sup.2 L cell a first intrinsic polysilicon layer is formed over the surface of the device cell, and N-type dopant is diffused through the polysilicon layer to form the N+ collectors of the NPN vertical transistors. Silicon oxide is formed over the doped polysilicon and the undoped intrinsic polysilicon is then removed. Exposed edge portions of the N doped polysilicon is then oxidized to completely insulate the surface of the polysilicon. A second layer of intrinsic polysilicon is then formed over the device cell and P type dopant is diffused through the second polysilicon layer to form the emitter and collector of a lateral PNP transistor and to contact the base regions of the NPN vertical transistors between the N+ collectors.

Abstract: An apparatus is described for maintaining and delivering a slack reserve length of lead wire between a spool or other source and the wire bonding tool of a lead wire bonding machine. A slack chamber or wind chamber comprised of a housing enclosure, an inlet guide on one side for guiding lead wire into the slack chamber from a spool, an outlet guide on the other side for guiding lead wire out of the slack chamber towards the wire bonding tool maintains the reserve length of lead wire in untangled condition. A source of pressurized dry air or other gas directs a gaseous flow into the slack chamber so that the lead wire is maintained suspended in the gaseous flow in an offset configuration. Wire sensors are operatively positioned in the slack chamber for sensing the offset of lead wire in the wind stream. The wire sensors are coupled to sensor and control logic for controlling the delivery and feeding of lead wire from a spool into the slack chamber.

Abstract: Manufacture of bipolar substantially isoplanar integrated circuit structures is accomplished by rearrangement of the conventional masking steps and by the substitution and full integration of implanting methods for diffusion methods. A uniform nitride layer is deposited over the basic structure of epitaxial islands separated by isolation oxide regions thereby passivating and protecting the isolation oxide regions, epitaxial oxide buffer layer and epitaxial layer from environmental contaminants. The nitride layer which forms part of a composite protective layer is maintained in place throughout a major portion of the fully integrated sequential implanting steps during which the collector sink, base and emitter regions are introduced into the epitaxial islands. At least a portion of the composite protective layer is a barrier to environmental contaminants throughout the process. The overall number of steps is reduced, etching steps minimized, and overall reliability of the structure improved.

Abstract: A low temperature insulating glass for use in semiconductor devices comprises a mixture of germanium, silicon, oxygen and phosphorus. In the preferred embodiment, the glass comprises a mixture of about 40% to 55% silicon dioxide (SiO.sub.2), about 55% to 40% of germanium dioxide (GeO.sub.2) and from 1% to about 5% of phosphorus pentoxide (P.sub.2 O.sub.5), by mole percent.

Abstract: A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PN junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

Abstract: A process and resulting structure are disclosed for forming vias in integrated circuit structures using metal silicide interconnections. A lower conductor is formed by sequentially depositing silicon and a refractory metal which reacts with the silicon to create a layer of metal silicide. A subsequent layer of silicon is deposited on the surface of the metal silicide. This layer of silicon is insulated from overlying layers by forming insulating material over desired regions of the layer of silicon. A second layer of metal is then deposited across the structure. In openings in the insulating material the metal reacts with the second layer of silicon to form a via of metal silicide. A final layer of silicon may be deposited to convert any remaining metal in the second layer of metal to metal silicide, and the structure annealed to lower its resistivity.

Abstract: Apparatus is provided for substituting a spare column of memory cells in a byte wide memory for a defective column of cells in such memory. The apparatus includes a spare column of memory cells, an electrically conductive line 13, a spare decoder 16 for switchably connecting the line 13 to the spare column, a first fuse FSD.sub.1 between the spare column and the line 13, a series of second fuses FS controlling a series of switches T.sub.1, T.sub.2 . . . between the line 13 and corresponding sense amplifiers 11, and a series of third fuses FD, each connected between a corresponding column and the sense amplifier associated with that column. The spare column of memory cells is connected to the appropriate sense amplifier by blowing the appropriate fuse FS and supplying the necessary address information to spare decoder 16. The defective column of memory cells may be disconnected by blowing the appropriate fuse FD.

Abstract: A circuit for use in controlling a memory cell coupled to a word line W and to first and second bit lines B1 and B2 includes an enabling flip-flop 20 having set terminal S connected to a source of enabling signals and a reset terminal R connected to an OR gate 22; a word line addressing circuit 25 connected to the output of the enabling flip-flop 20 and to the word line W, and having a terminal ADDR for receiving address information; first and second read/write circuits 29 and 30 connected to corresponding first and second bit lines B1 and B2, respectively, each of the read/write circuits 29 and 30 including a control node WRC and an output node SADO; a logic gate 22 having an output coupled to the reset terminal and having input nodes SADO 0 and SADO 1 connected to the corresponding output nodes of the read/write circuits 29 and 30, and an output flip-flop 33 connected the output nodes SADO 0 and SADO 1 of the read/write circuits 29 and 30.

Abstract: In a microprocessor having independent address and data paths and other pipeline architecture features, a control unit utilizes a PLA which stores microcoded instruction sequences. These sequences permit an operator at a console to read data from and write data to all the internal registers, any external memory location or the program counter. In addition, the PLA contains microcode which enables programs in external memory to be loaded from any location in memory and run by command from the console as well as to enable the operator to halt user program execution, read the pertinent internal registers, and then continue program execution such that single step execution for debug purposes is possible.

Abstract: A method, timing control circuit, and power supply are described for initiating arc discharge between the cover gas delivery shroud and lead wire held in the bonding tool of a lead wire bonding machine for melting and forming a ball at the end of the lead wire. An arc discharge timing control pulse controls duration of the arc discharge within an empirically determined time window between the shortest and longest durations of arc discharge which result in optimal ball formation of a substantially spherical ball at the end of the lead wire without necking of the lead wire above the formed ball. The timing control circuit also provides an initial cover gas movement delay before ball formation for displacing oxygen from the shield and the end of the lead wire, and a subsequent cooling delay for solidifying and cooling the formed ball in the cover gas stream prior to ball bonding.

Abstract: An improved tristate enable circuit is described for activating a tristate enable gate to maintain the high impedance third state of a common bus tristate output device during "power down" and "power up" transitions of the common power supply V.sub.cc. The enable gate circuit element tends to turn off at a voltage level V.sub.cc2 generally greater than the voltage level V.sub.cc3 at which the tristate output device circuit elements turn off. As a result the high impedance state may be lost during "power down". A threshold activation circuit is coupled to the enable gate for activating the enable gate when the threshold activation circuit senses a higher common power supply voltage level V.sub.cc1. The threshold activation circuit operatively activates the enable gate over a voltage range from V.sub.cc1 to a lesser common power supply voltage level V.sub.cc4. Component values are selected for relating the voltage levels so that V.sub.cc1 >V.sub.cc2 and V.sub.cc3 >V.sub.cc4.

Abstract: A structure and method are provided wherein a single output buffer stage (50) is provided which can be programmed to function either as an open drain output buffer or a CMOS Push-Pull output buffer. The output buffer stage constructed in accordance with this invention is programmed in one of several manners. In one embodiment of this invention, the fabrication steps utilized to program the output buffer are the enhancement and depletion dopings, whereby certain devices of the output buffer are programmed to either remain always turned off or always turned on, thus programming the output buffer to serve either as an open drain output buffer or as a CMOS push-pull output buffer.

Abstract: In a capacitive storage integrated circuit dynamic random access memory having a cross-coupled transistor sense amplifier coupled to a bit line wherein capacitive storage cells are coupled to the bit line through transistor transfer gates, means are provided for restoring charge on the capacitive storage cell by recharging the memory cells directly rather than through the bit lines. Specifically, each storage cell has one terminal coupled to one electrode terminal of the transistor transfer gate and its other terminal coupled to a switched voltage reference. The storage cell is not referenced to a fixed ground level.

Abstract: Circuitry for rapidly discharging a row of RAM cells upon deselection of the word line. The word line switching transistor collector current is sensed and corresponding voltage level signals are applied to a second switching transistor between the bottom word line of the memory row and a large dump current source. The emitter of the second switching transistor is clamped at a level that will permit the switching transistor to turn on only when there is no emitter current through the word line switching transistor to thereby rapidly discharge the capacitive row of memory cells and therefore improve the operating speed of the memory.

Abstract: Apparatus and method are described for rapid ball formation at the end of lead wire retained in the capillary wire holding tool of a ball bonding machine. A circuit is coupled between the cover gas shroud and lead wire for establishing controlled electrical discharge between the end of the bonding wire and the shroud, for melting and forming a ball. The circuit includes a DC power supply for delivering a positive polarity to the shroud and negative polarity to the lead wire for drawing a discharge of electrons from the end of the lead wire to the shroud. A capacitor is coupled in series with the DC power supply for receiving the electrical discharge. An impedance is also coupled in series for limiting the electrical discharge current. Charging of the capacitor limits and shapes the electrical arc discharge to a controlled pulse profile of short duration for rapid ball formation. An electronic gate is also used to control pulse duration.

Abstract: A method and apparatus is disclosed for forming a ball at the end of bonding wire or lead wire held in a capillary wire holding and bonding tool for ball bonding of the lead wire to an integrated circuit chip. The method of ball formation is of the type in which the end of the bonding wire is enclosed in a shroud or shield and the shield and the end of the bonding wire are flooded with an inert cover gas. Ball formation is accomplished by electrically discharging an arc between the bonding wire and the shroud for melting and forming the ball at the end of the wire. A passageway is provided for delivering and mixing hydrogen gas into the inert cover gas delivery line at a location upstream from the shroud sufficient for complete mixing. The rate of flow of hydrogen gas is metered and controlled for adjusting the percent by volume of hydrogen in the cover gas mixture to a desired range.

Abstract: A programmable address buffer for coupling external addresses to a desired pair of internal memory addresses includes A and B address inputs 11 and 12, a B address output 15 coupled to the B address input 12, a first inverter I30 coupled to the B address input and a B address output, a first switch S2 coupled to switchably connect one of the A and B address inputs 11 and 12 to a node, an A address output coupled to the first node, a second inverter I10 connected to the first node, a third inverter I20 connected between the second node and an A output 14, and a second switch S1 coupled to the second node to switchably connect one of the first node or the second inverter I10 to the second node.In another embodiment an electrical circuit for controlling the addressing of functional sections of a partially functional product includes a first pin 100 coupled by a first fuse F.sub.1 to a first address buffer 150, and a second pin 110 coupled by a second fuse F.sub.

Abstract: A power transistor array integrated circuit includes an array of transistors, each having an electrode connected in common to a conductive line forming a part of the integrated circuit. The electrodes of the transistors are spaced along the conductive line and have a decreasing length in a given direction along the conductive line and have a decreasing length in a given direction along the conductive line. The conductive line has a corresponding increasing width in the given direction. The decrease in length of the electrode and the increase in width of the conductive line are such that the electrodes and the conductive line form a generally rectangular shape. Differences in turn-on voltage for the transistors resulting from the differences in their electrode length tend to compensate for voltage drop in the conductive line, thus giving uniform outputs from the transistors in the array.