Abstract: Silicon carbide (SiC) is used as the stop layer for the chemical-mechanical polishing used to planarize the surface of interlevel dielectrics, making the resistance of the vias more uniform. Alternatively, silicon carbonitride or silicon carboxide can be used in place of silicon carbide.

Abstract: A ferroelectric capacitor electrode contact structure comprising an insulator (4) placed over a substrate (2) and containing a transistor source (6) and transistor drain (8) between the substrate (2) and the insulator (4). The insulator (4) contains a source plug (10) and a conductive drain plug (12). The transistor source (6) is electrically connected to the source plug (10). The transistor drain (8) is electrically connected to the conductive drain plug (12). A transistor gate (14) is between the source plug (10) and a conductive drain plug (12) and is contained by the insulator (4). Metal wiring (16) is electrically connected to the source plug (10). A barrier film (18) is placed over the insulator (4) and the conductive drain plug (12). The bottom electrode (20) is placed over the barrier film (18). The ferroelectric layer (22) is placed over the bottom electrode (20). The top electrode (24) is placed over the ferroelectric layer (22).

Abstract: A thermal neutron shield (520) for integrated circuits (511-515) deters absorption of thermal neutrons by circuit constituents to form unstable isotopes with subsequent decay which generates bursts of charge which may upset of stored charge and create soft errors. The shielding may be either at the integrated circuit level (such as a layer on insulation or in the filler of plastic packaging material) or at the board level (such as a filler or film on a container wall).

Abstract: A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).

Abstract: A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.

Abstract: A plasma process is described which produces an undamaged and uncontaminated silicon surface by consuming silicon by continuous oxidation through a surface oxide layer and a simultaneous etch of the exposed silicon oxide surface. The surface silicon dioxide layer thickness is controlled as an equilibrium between oxide growth from oxygen atoms reaching the silicon surface and etching of the oxide surface. The silicon dioxide protects the silicon surface from plasma damage and from contamination.

Abstract: Pulsed plasma deposition of polymers as dielectrics for integrated circuit interconnects fills minimal gaps and yields a porous polymer with thermal stability by plasma off times sufficiently long to dissipate plasma on time energy input plus an anneal of the deposited polymer to drive off occluded monomers and small oligomers.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A power supply (500) with vertical field effect transistor synchronous rectifiers (VFET1 and VFET2) having drivers (VFET Driver1 and VFET Driver2) which provide bipolar mode of operation by diode clamping an inductor overshoot which forwards biases the gate-source junction. The rectifiers have low on resistance useful in low output voltage power supplies.

Abstract: A programmable memory device having slot trenches (14). A plurality of floating gates (22) are separated from a surface of semiconductor body (10) by a gate dielectric (24). A plurality of slot trenches (14) isolate memory cells (12) from each other. Each of the slot trenches (14) extends below the surface of the semiconductor body (10) between adjacent floating gates (22). A control gate (20) extends over the floating gates (22) and a portion of each of the slot trenches (14).

Abstract: A strip for TiN with selectivity to TiSi2 consisting of a water solution of H2O2 with possible small amounts of NH4OH.

Abstract: A quantum transistor (10) includes an emitter (38), an injector structure (36), a base (20) and a collector (16) coupled to the base. The injector (36) is interposed between the emitter (38) and the base (20). The injector structure (36) includes a quantum well (60) having a general conductance band minimum energy level. A notch (28) in the well (60) has a conductance band minimum energy level that is lower than the general level. This notch (28) is operable to lower the energy of electrons disposed in the quantum well (60). Therefore, the electrons resident in the well are injected through a barrier (24) into the base (20) at an energy level at or slightly above the base/collector barrier &phgr;BC, but below the X or L energies such that intervalley scattering is reduced.

Abstract: A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Abstract: A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors.

Abstract: A method and structure for etching a thin film perovskite layer (e.g., barium strontium titanate 836) overlying a second material without substantially etching the second material. The method comprises forming a substantially-silicon-free dielectric etchstop layer (e.g., aluminum nitride 858) on a second dielectric layer comprising silicon (e.g., silicon dioxide 818), depositing the perovskite layer over the etchstop layer, forming a mask layer (e.g., photoresist 842) over the perovsklte layer, patterning and removing portions of the mask layer to form a desired pattern, and etching portions of the perovskite layer not covered by the mask layer, whereby the etching stops on the etchstop layer. The structure comprises a substantially-silicon-free dielectric etchstop layer overlying a second dielectric layer comprising silicon, and a perovskite layer having a desired pattern and comprising an etched side overlying a substantially unetched portion of the etchstop layer.

Abstract: Serial data processor (16) includes a digital processor (106) , a memory controller (114) interconnected with digital processor (106), and dynamic serial access memory (112) interconnected with memory controller(134) . First data selection circuit (134) sends serial data either from serial-data-in terminal (94), from dynamic serial access memory (112), or from digital processor (106) to second serial-data-in terminal (138), in response to a first control signal. Second data selection circuit (144) sends serial data either from serial-data-in terminal (138), from dynamic serial access memory (132) or from the digital processor to serial-data-out terminal (96), in response to a second control signal. A third data selection circuit (120) sends serial data either from serial-data-in terminal (94) , from dynamic serial access memory (112), or from the digital processor (90) to third serial-data-in terminal (150), in response to a third control signal.

Abstract: A circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a first terminal coupled to a power supply and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well 504 and a shunting bipolar transistor is formed between the n-well 504 and an n-doped guard ring 500 formed adjacent to the n-well in the p-doped substrate 508.

Abstract: A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer 824 between the platinum layer and the second material; forming a hardmask layer 829 over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer 832, the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti--Al--N including at least 1% of aluminum.

Abstract: Intermetal level dielectrics comprise fluorinated polydimethylenenaphthalene derived from the following monomers wherein each of R.sub.1, R.sub.2, R.sub.3, and R.sub.4 is selected from the group consisting of H, F, and fluorocarbon groups ##STR1## The dielectric and oxides may be between metal lines. Fluorination of the polydimethylenenaphthalene lowers dielectric constant and increases working temperature.

Abstract: A bridge circuit uses active feedback to control drive phase turn on to substantially eliminate shoot-through current. Voltage sensor 66 senses H-bridge transistor voltage turn off levels and causes control circuit 64 to latch which causes enable circuit 62 to allow the next phase of H-bridge transistor turn on. A critical aspect of the invention is to ensure all H-bridge transistors are off before the enable circuit allows the next phase to turn any H-bridge transistors on.